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| author | Stephen Boyd <sboyd@kernel.org> | 2024-09-03 14:00:29 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2024-09-03 14:00:29 -0700 |
| commit | f37213104a370ca60d9c475519b30c848c6d7d6d (patch) | |
| tree | 98b230795f7adcefccb97c7eae80f46780d89492 /tools/perf/scripts/python/netdev-times.py | |
| parent | b01bf907bd9cdf5810397e9f831c3ecebc4a4ce8 (diff) | |
| parent | 3aeccbe08171b79f82fb802393a6324c7b732669 (diff) | |
Merge tag 'renesas-clk-for-v6.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull more Renesas clk driver updates from Geert Uytterhoeven:
- Add USB clocks, resets and power domains on RZ/G3S
- Add Generic Timer (GTM), I2C Bus Interface (RIIC), SD/MMC Host
Interface (SDHI) and Watchdog Timer (WDT) clocks and resets on
RZ/V2H
- Miscellaneous fixes and improvements
* tag 'renesas-clk-for-v6.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT
clk: renesas: rzv2h: Add support for dynamic switching divider clocks
clk: renesas: r9a08g045: Add clocks, resets and power domains for USB
dt-bindings: clock: renesas,cpg-clocks: Add top-level constraints
Diffstat (limited to 'tools/perf/scripts/python/netdev-times.py')
0 files changed, 0 insertions, 0 deletions