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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2024-08-28 10:38:22 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-09-02 10:15:38 +0200 |
| commit | 3aeccbe08171b79f82fb802393a6324c7b732669 (patch) | |
| tree | 98b230795f7adcefccb97c7eae80f46780d89492 /tools/perf/scripts/python/netdev-times.py | |
| parent | bc4d25fdfadfa80dc3ba690792b5220d50ea7b52 (diff) | |
clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT
Add clock and reset entries for Generic Timer (GTM), I2C Bus Interface
(RIIC), SD/MMC Host Interface (SDHI) and Watchdog Timer (WDT) IP blocks.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240828093822.162855-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/netdev-times.py')
0 files changed, 0 insertions, 0 deletions