diff options
author | Stephen Boyd <sboyd@kernel.org> | 2024-08-27 10:20:46 -0700 |
---|---|---|
committer | Stephen Boyd <sboyd@kernel.org> | 2024-08-27 10:20:46 -0700 |
commit | b01bf907bd9cdf5810397e9f831c3ecebc4a4ce8 (patch) | |
tree | c5f2d3a84168fa16642af1f44e718045b3621f72 /tools/perf/scripts/python/netdev-times.py | |
parent | 8400291e289ee6b2bf9779ff1c83a291501f017b (diff) | |
parent | 120c2833b72f4bdbd67ea2cf70b9d96d1c235717 (diff) |
Merge tag 'renesas-clk-for-v6.12-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven
- Add PCIe, PWM, and CAN-FD clocks on R-Car V4M
- Add LCD controller clocks and resets on RZ/G2UL
- Add DMA clocks and resets on RZ/G3S
- Add fractional multiplication PLL support on R-Car Gen4
- Document support for the Renesas RZ/G2M v3.0 (r8a774a3) SoC
- Add support for the RZ/V2H(P) (R9A09G057) SoC
- Miscellaneous fixes and improvements
* tag 'renesas-clk-for-v6.12-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (30 commits)
clk: renesas: r8a779h0: Add CANFD clock
clk: renesas: Add RZ/V2H(P) CPG driver
clk: renesas: Add family-specific clock driver for RZ/V2H(P)
dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG
clk: renesas: r8a779h0: Add PWM clock
dt-bindings: clock: renesas,cpg-mssr: Document RZ/G2M v3.0 (r8a774a3) clock
clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs
clk: renesas: rcar-gen4: Remove unused fixed PLL clock types
clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type
clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLs
clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLs
clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLs
clk: renesas: r8a779a0: Use defines for PLL control registers
clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLs
clk: renesas: rcar-gen4: Add support for fixed variable PLLs
clk: renesas: rcar-gen4: Add support for variable fractional PLLs
clk: renesas: rcar-gen4: Add support for fractional multiplication
clk: renesas: rcar-gen4: Use defines for common CPG registers
clk: renesas: rcar-gen4: Use FIELD_GET()
clk: renesas: rcar-gen4: Clarify custom PLL clock support
...
Diffstat (limited to 'tools/perf/scripts/python/netdev-times.py')
0 files changed, 0 insertions, 0 deletions