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path: root/drivers/phy/qualcomm/Kconfig
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2023-12-04phy: qcom: qmp-combo: switch to DRM_AUX_BRIDGEDmitry Baryshkov1-1/+1
Switch to using the new DRM_AUX_BRIDGE helper to create the transparent DRM bridge device instead of handcoding corresponding functionality. Acked-by: Vinod Koul <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-22phy: qcom: Introduce M31 USB PHY driverVaradarajan Narayanan1-0/+11
Add the M31 USB2 phy driver for the USB M31 PHY (https://www.m31tech.com) found in Qualcomm IPQ5018, IPQ5332 SoCs. Signed-off-by: Varadarajan Narayanan <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/c8821bb0124a54cc774a2ff7b9c40df28eb7711e.1691999761.git.quic_varada@quicinc.com Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom-qmp-usb: split off the legacy USB+dp_com supportDmitry Baryshkov1-0/+10
When adding support for some of the platforms (sc7180, sc8180x, sdm845, sm8[1234]50), we added USB PHYs for the combo USB+DP QMP PHYs. Now all such usecases were migrated to use USB+DP Combo driver. To simplify the qcom-qmp-usb PHY driver split the legacy USB+dp_com support into a separate driver. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-06-21phy: qcom: add the SGMII SerDes PHY driverBartosz Golaszewski1-0/+9
Implement support for the SGMII/SerDes PHY present on various Qualcomm platforms. Signed-off-by: Bartosz Golaszewski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-05-19phy: qcom-qmp-combo: Introduce drm_bridgeBjorn Andersson1-0/+2
The QMP combo PHY sits in an of_graph connected between the DisplayPort controller and a USB Type-C connector (or possibly a redriver). The TCPM needs to be able to convey the HPD signal to the DisplayPort controller, but no directly link is provided by DeviceTree so the signal needs to "pass through" the QMP combo phy. Handle this by introducing a drm_bridge which upon initialization finds the next bridge (i.e. the usb-c-connector) and chain this together. This way HPD changes in the connector will propagate to the DisplayPort driver. The connector bridge is resolved lazily, as the TCPM is expected to be able to resolve the typec mux and switch at probe time, so the QMP combo phy will probe before the TCPM. Acked-by: Neil Armstrong <[email protected]> Tested-by: Bryan O'Donoghue <[email protected]> Reviewed-by: Bryan O'Donoghue <[email protected]> Tested-by: Abel Vesa <[email protected]> Tested-by: Steev Klimaszewski <[email protected]> Tested-by: Neil Armstrong <[email protected]> # on HDK8450 Tested-by: Johan Hovold <[email protected]> # X13s Reviewed-by: Johan Hovold <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-05-19phy: qcom-qmp-combo: Introduce orientation switchingBjorn Andersson1-0/+1
The data lanes of the QMP PHY is swapped in order to handle changing orientation of the USB Type-C cable. Register a typec_switch device to allow a TCPM to configure the orientation. The newly introduced orientation variable is adjusted based on the request, and the initialized components are brought down and up again. To keep track of what parts needs to be cycled new variables to keep track of the individual init_count is introduced. Both the USB and the DisplayPort altmode signals are properly switched. For DisplayPort the controller will after the TCPM having established orientation power on the PHY, so this is not done implicitly, but for USB the PHY typically is kept initialized across the switch, and must therefore then be reinitialized. This is based on initial work by Wesley Cheng. Link: https://lore.kernel.org/r/[email protected]/ Reviewed-by: Johan Hovold <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Tested-by: Abel Vesa <[email protected]> Tested-by: Steev Klimaszewski <[email protected]> Tested-by: Neil Armstrong <[email protected]> # on HDK8450 Tested-by: Johan Hovold <[email protected]> # X13s Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-02-16phy: qcom: Add QCOM SNPS eUSB2 repeater driverAbel Vesa1-0/+9
PM8550B contains a eUSB2 repeater used for making the eUSB2 from SM8550 USB 2.0 compliant. This can be modelled SW-wise as a Phy. So add a new phy driver for it. Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-02-10phy: qcom: Add QCOM SNPS eUSB2 driverAbel Vesa1-0/+9
The SM8550 SoC uses Synopsis eUSB2 PHY for USB 2.0. Add a new driver for it. The driver is based on a downstream implementation. Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-02-03phy: qcom-qmp: Introduce Kconfig symbols for discrete driversStephen Boyd1-4/+46
Introduce a config option for each QMP PHY driver now that the QMP PHY mega-driver has been split up into different modules. This allows kernel configurators to limit the binary size of the kernel by only compiling in the QMP PHY driver that they need. Leave the old config QCOM_QMP in place and make it into a menuconfig so that 'make olddefconfig' continues to work. Furthermore, set the default of the new Kconfig symbols to be QCOM_QMP so that the transition is smooth. Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Signed-off-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-11-10phy: qcom-qmp-pcie: add support for sc8280xp 4-lane PHYsJohan Hovold1-0/+1
The PCIe2 and PCIe3 controllers and PHYs on SC8280XP can be used in 4-lane mode or as separate controllers and PHYs in 2-lane mode (e.g. as PCIe2A and PCIe2B). Add support for fetching the 4-lane configuration from the TCSR and programming the lane registers of the second port when in 4-lane mode. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-11-23phy: qcom: Introduce new eDP PHY driverBjorn Andersson1-0/+10
Many recent Qualcomm platforms comes with native DP and eDP support. This consists of a controller in the MDSS and a QMP-like PHY. While similar to the well known QMP block, the eDP PHY only has TX lanes and the programming sequences are slightly different. Rather than continuing the trend of parameterize the QMP driver to pieces, this introduces the support as a new driver. The registration of link and pixel clocks are borrowed from the QMP driver. The non-DP link frequencies are omitted for now. The eDP PHY is very similar to the dedicated (non-USB) DP PHY, but only the prior is supported for now. Signed-off-by: Bjorn Andersson <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2020-11-16phy: qualcomm: Fix 28 nm Hi-Speed USB PHY OF dependencyBryan O'Donoghue1-1/+1
This Kconfig entry should declare a dependency on OF Fixes: 67b27dbeac4d ("phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driver") Signed-off-by: Bryan O'Donoghue <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2020-11-16phy: qualcomm: usb: Fix SuperSpeed PHY OF dependencyBryan O'Donoghue1-1/+1
This Kconfig entry should declare a dependency on OF Fixes: 6076967a500c ("phy: qualcomm: usb: Add SuperSpeed PHY driver") Reported-by: kernel test robot <[email protected]> Link: https://lkml.org/lkml/2020/11/13/414 Signed-off-by: Bryan O'Donoghue <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2020-07-20phy: qualcomm: add qcom ipq806x dwc usb phy driverAnsuel Smith1-0/+10
This has lost in the original push for the dwc3 qcom driver. This is needed for ipq806x SoC as without this the usb ports doesn't work at all. Signed-off-by: Andy Gross <[email protected]> Signed-off-by: Ansuel Smith <[email protected]> Tested-by: Jonathan McDowell <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2020-07-08phy: qcom: remove ufs qmp phy driverVinod Koul1-24/+0
The UFS specific QMP PHY driver started off supporting the 14nm and 20nm hardware. With the 20nm support marked broken for a long time and the 14nm support added to the common QMP PHY, this driver has not been used in a while. So delete it Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2020-05-05phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCsWesley Cheng1-0/+10
This adds the SNPS FemtoPHY V2 driver used in QCOM SOCs. There are potentially multiple instances of this UTMI PHY on the SOC, all which can utilize this driver. The V2 driver will have a different register map compared to V1. Signed-off-by: Wesley Cheng <[email protected]> Reviewed-by: Philipp Zabel <[email protected]> Reviewed-by: Manu Gautam <[email protected]> Reviewed-by: Vinod Koul <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2020-05-04phy: add driver for Qualcomm IPQ40xx USB PHYRobert Marko1-0/+7
Add a driver to setup the USB PHY-s on Qualcom m IPQ40xx series SoCs. The driver sets up HS and SS phys. Signed-off-by: John Crispin <[email protected]> Signed-off-by: Robert Marko <[email protected]> Cc: Luka Perkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2020-03-20phy: qualcomm: usb: Add SuperSpeed PHY driverJorge Ramirez-Ortiz1-0/+9
Controls Qualcomm's SS PHY 1.0.0 implemented on various SoCs on both the 20nm and 28nm process nodes. Based on Sriharsha Allenki's <[email protected]> original code. [bod: Removed dependency on extcon. Switched to gpio-usb-conn to handle VBUS On/Off Switched to usb-role-switch to bind gpio-usb-conn to DWC3] Signed-off-by: Jorge Ramirez-Ortiz <[email protected]> Cc: Jorge Ramirez-Ortiz <[email protected]> Cc: Sriharsha Allenki's <[email protected]> Cc: Andy Gross <[email protected]> Cc: Bjorn Andersson <[email protected]> Cc: Kishon Vijay Abraham I <[email protected]> Cc: Philipp Zabel <[email protected]> Cc: [email protected] Cc: [email protected] Reviewed-by: Philipp Zabel <[email protected]> Tested-by: Bjorn Andersson <[email protected]> Signed-off-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driverShawn Guo1-0/+11
Adds Qualcomm 28nm Hi-Speed USB PHY driver support. This PHY is usually paired with Synopsys DWC3 USB controllers on Qualcomm SoCs. The PHY can come in two flavours femtoPHY or picoPHY. This commit adds support for the femtoPHY with the possibility of extending to the picoPHY with additional future commits. Both PHYs are on a 28 nanometer process node. [bod: Updated qcom_snps_hsphy_set_mode to match new method signature Added disjunct on mode > 0 Removed regulator_set_voltage() in favour of setting floor in dts Removed 'snps' and from driver name Extended commit log to mention femtoPHY and picoPHY for future reference.] Signed-off-by: Shawn Guo <[email protected]> Cc: Andy Gross <[email protected]> Cc: Bjorn Andersson <[email protected]> Cc: Kishon Vijay Abraham I <[email protected]> Cc: Philipp Zabel <[email protected]> Cc: Jorge Ramirez-Ortiz <[email protected]> Cc: [email protected] Cc: [email protected] Tested-by: Bjorn Andersson <[email protected]> Signed-off-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2019-07-01Merge tag 'phy-for-5.3' of ↵Greg Kroah-Hartman1-0/+8
git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next phy: for 5.3 *) Add a new PHY driver for Qualcomm PCIe2 PHY *) Add a new PHY driver for Mixel DPHY present in i.MX8 *) Fix Qualcomm QMP UFS PHY driver from incorrectly reporting that PHY enable failed *) Fix _BUG_ on Amlogic G12A USB3 + PCIE Combo PHY Driver due to calling a sleeping function from invalid context *) Fix WARN_ON dump on rcar-gen3-usb2 PHY driver caused due to imbalance powered flag *) Fix .cocci and sparse warnings Signed-off-by: Kishon Vijay Abraham I <[email protected]> * tag 'phy-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: phy: qcom-qmp: Raise qcom_qmp_phy_enable() polling delay phy: meson-g12a-usb3-pcie: disable locking for cr_regmap phy: Add driver for mixel mipi dphy found on NXP's i.MX8 SoCs dt-bindings: phy: Add documentation for mixel dphy dt-bindings: phy-pxa-usb: add bindings phy: renesas: rcar-gen3-usb2: fix imbalance powered flag phy: qcom-qmp: Drop useless msm8998_pciephy_cfg setting phy: qcom-qmp: Correct READY_STATUS poll break condition phy: ti: am654-serdes: Make serdes_am654_xlate() static phy: usb: phy-brcm-usb: Fix platform_no_drv_owner.cocci warnings phy: samsung: Use struct_size() in devm_kzalloc() phy: qcom: Add Qualcomm PCIe2 PHY driver dt-bindings: phy: Add binding for Qualcomm PCIe2 PHY
2019-05-31phy: qcom: Add Qualcomm PCIe2 PHY driverBjorn Andersson1-0/+8
The Qualcomm PCIe2 PHY is based on design from Synopsys and found in several different platforms where the QMP PHY isn't used. Reviewed-by: Niklas Cassel <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner1-0/+1
Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-09-26phy: qcom-ufs: Declare 20nm qcom ufs qmp phy as BrokenVivek Gautam1-0/+17
Fork out separate configs for 14nm and 20nm qcom ufs qmp phys to declare the 20nm phy as broken. Signed-off-by: Vivek Gautam <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2018-04-25phy: Add a driver for the ATH79 USB phyAlban Bedel1-1/+10
The ATH79 USB phy is very simple, it only have a reset. On some SoC a second reset is used to force the phy in suspend mode regardless of the USB controller status. This driver is added to the qualcom directory as atheros is now part of qualcom and newer SoC of this familly are marketed under the qualcom name. Signed-off-by: Alban Bedel <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2017-06-01phy: Group vendor specific phy driversVivek Gautam1-0/+58
Adding vendor specific directories in phy to group phy drivers under their respective vendor umbrella. Also updated the MAINTAINERS file to reflect the correct directory structure for phy drivers. Signed-off-by: Vivek Gautam <[email protected]> Acked-by: Heiko Stuebner <[email protected]> Acked-by: Viresh Kumar <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Acked-by: Yoshihiro Shimoda <[email protected]> Reviewed-by: Jaehoon Chung <[email protected]> Cc: Kishon Vijay Abraham I <[email protected]> Cc: David S. Miller <[email protected]> Cc: Geert Uytterhoeven <[email protected]> Cc: Yoshihiro Shimoda <[email protected]> Cc: Guenter Roeck <[email protected]> Cc: Heiko Stuebner <[email protected]> Cc: Viresh Kumar <[email protected]> Cc: Maxime Ripard <[email protected]> Cc: Chen-Yu Tsai <[email protected]> Cc: Sylwester Nawrocki <[email protected]> Cc: Krzysztof Kozlowski <[email protected]> Cc: Jaehoon Chung <[email protected]> Cc: Stephen Boyd <[email protected]> Cc: Martin Blumenstingl <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Signed-off-by: Kishon Vijay Abraham I <[email protected]>
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