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path: root/drivers/net/ethernet/intel/ice/ice_ptp_consts.h
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2024-06-01ice: Add support for E825-C TS PLL handlingMichal Michalik1-0/+87
The CGU layout of E825-C is a little different than E822/E823. Add support the new hardware adding relevant functions. Signed-off-by: Michal Michalik <[email protected]> Reviewed-by: Przemek Kitszel <[email protected]> Reviewed-by: Arkadiusz Kubalewski <[email protected]> Signed-off-by: Karol Kolacinski <[email protected]> Tested-by: Pucha Himasekhar Reddy <[email protected]> Signed-off-by: Jacob Keller <[email protected]> Link: https://lore.kernel.org/r/20240528-next-2024-05-28-ptp-refactors-v1-9-c082739bb6f6@intel.com Signed-off-by: Jakub Kicinski <[email protected]>
2024-06-01ice: Introduce ETH56G PHY model for E825C productsSergey Temerkhanov1-0/+315
E825C products feature a new PHY model - ETH56G. Introduces all necessary PHY definitions, functions etc. for ETH56G PHY, analogous to E82X and E810 ones with addition of a few HW-specific functionalities for ETH56G like one-step timestamping. It ensures correct PTP initialization and operation for E825C products. Co-developed-by: Jacob Keller <[email protected]> Signed-off-by: Jacob Keller <[email protected]> Co-developed-by: Michal Michalik <[email protected]> Signed-off-by: Michal Michalik <[email protected]> Signed-off-by: Sergey Temerkhanov <[email protected]> Reviewed-by: Przemek Kitszel <[email protected]> Reviewed-by: Arkadiusz Kubalewski <[email protected]> Co-developed-by: Karol Kolacinski <[email protected]> Signed-off-by: Karol Kolacinski <[email protected]> Tested-by: Pucha Himasekhar Reddy <[email protected]> Signed-off-by: Jacob Keller <[email protected]> Link: https://lore.kernel.org/r/20240528-next-2024-05-28-ptp-refactors-v1-7-c082739bb6f6@intel.com Signed-off-by: Jakub Kicinski <[email protected]>
2023-12-05ice: Rename E822 to E82XKarol Kolacinski1-6/+6
When code is applicable for both E822 and E823 devices, rename it from E822 to E82X. ICE_PHY_PER_NAC_E822 was unused, so just remove it. Signed-off-by: Karol Kolacinski <[email protected]> Reviewed-by: Przemek Kitszel <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Tony Nguyen <[email protected]> Signed-off-by: Paolo Abeni <[email protected]>
2021-12-21ice: ensure the hardware Clock Generation Unit is configuredJacob Keller1-0/+74
The E822 device has a Clock Generation Unit (CGU) responsible for determining the clock frequency that drives the timers. Ensure this function is initialized when bringing up the PTP support, so that the clock has a known frequency. Signed-off-by: Jacob Keller <[email protected]> Tested-by: Gurucharan G <[email protected]> Signed-off-by: Tony Nguyen <[email protected]>
2021-12-21ice: implement basic E822 PTP supportJacob Keller1-0/+300
Implement support for the basic operations needed to enable the PTP hardware clock on E822 devices. This includes implementations for the various PHY access functions, as well as the ability to start and stop the PHY timers. This is different from the E810 device because the configuration depends on link speed, so we cannot just start the PHYs immediately. We must wait until the link is up to get proper values for the speed based initialization. Signed-off-by: Jacob Keller <[email protected]> Tested-by: Gurucharan G <[email protected]> Signed-off-by: Tony Nguyen <[email protected]>
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