| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2024-08-13 | drm/amdgpu/uvd4: fix mask and shift definitions | Remington Brasga | 1 | -2/+0 | |
| A few define's are listed twice with different, incorrect values. This fix sets them appropriately. Signed-off-by: Remington Brasga <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2020-09-17 | drm/amd/amdgpu: add mmUVD_FW_STATUS register to uvd700 | Tom St Denis | 2 | -0/+23 | |
| This register was requested for umr debugging support. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2020-07-01 | drm amdgpu: SI UVD registers | Sonny Jiang | 2 | -0/+902 | |
| Add SI UVD registers files. Signed-off-by: Sonny Jiang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2017-12-06 | drm/amd/include:cleanup vega10 uvd header files. | Feifei Xu | 2 | -0/+1033 | |
| Cleanup asic_reg/vega10/UVD folder,remove unused uvd_7_0_default.h. Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2017-10-06 | drm/amdgpu: add uvd enc registers in header | James Zhu | 1 | -0/+15 | |
| Add UVD encode write/read/size/base registers definition for uvd6.3 HEVC ecoding Signed-off-by: James Zhu <[email protected]> Reviewed-and-Tested-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2016-11-11 | drm/amd/amdgpu: Introduction of SI registers (v2) | Tom St Denis | 2 | -0/+891 | |
| This introduces the SI registers in the amdgpu driver style. v2: squash duplicates fix Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2016-08-24 | drm/amdgpu: switch UVD code to use UVD_NO_OP for padding | Alex Deucher | 2 | -0/+2 | |
| Replace packet2's with packet0 writes to UVD_NO_OP. The value written to UVD_NO_OP does not matter. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2016-08-24 | drm/amdgpu: add support for UVD_NO_OP register | Alex Deucher | 1 | -0/+1 | |
| Writes to this register are the preferred way to do NOPs. Bump the driver version as well. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2016-07-29 | drm/amdgpu: implement UVD VM mode for Stoney v2 | Christian König | 1 | -0/+2 | |
| Starting with Stoney we support running UVD in VM mode as well. v2: rebased, only enable on Polaris for now. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2016-05-04 | drm/amdgpu: handle more than 10 UVD sessions (v2) | Arindam Nath | 1 | -0/+1 | |
| Change History -------------- v2: - Make firmware version check correctly. Firmware versions >= 1.80 should all support 40 UVD instances. - Replace AMDGPU_MAX_UVD_HANDLES with max_handles variable. v1: - The firmware can handle upto 40 UVD sessions. Signed-off-by: Arindam Nath <[email protected]> Signed-off-by: Ayyappa Chandolu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2015-06-03 | drm/amdgpu: add UVD 6.0 register headers | Alex Deucher | 3 | -0/+2230 | |
| These are register headers for the UVD (Universal Video Decoder) block on the GPU. Acked-by: Christian König <[email protected]> Acked-by: Jammy Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2015-06-03 | drm/amdgpu: add UVD 5.0 register headers | Alex Deucher | 3 | -0/+2371 | |
| These are register headers for the UVD (Universal Video Decoder) block on the GPU. Acked-by: Christian König <[email protected]> Acked-by: Jammy Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2015-06-03 | drm/amdgpu: add UVD 4.2 register headers | Alex Deucher | 2 | -0/+895 | |
| These are register headers for the UVD (Universal Video Decoder) block on the GPU. Acked-by: Christian König <[email protected]> Acked-by: Jammy Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||