| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2016-11-11 | drm/amd/amdgpu: add SI defines/registers | Tom St Denis | 1 | -0/+24 | |
| Add missing gca MMIO registers and defines necessary for the next patch which re-works a lot of gfx v6 to use the new SI headers. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2016-11-11 | drm/amd/amdgpu: Introduction of SI registers (v2) | Tom St Denis | 2 | -0/+14581 | |
| This introduces the SI registers in the amdgpu driver style. v2: squash duplicates fix Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2016-07-07 | drm/amd/powerplay: add shared definitions for di/dt feature. | Rex Zhu | 2 | -0/+83 | |
| v1: delete some comflict definitions between polaris and fiji. Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2016-07-07 | drm/amdgpu: remove gfx8 registers that vary between asics | Ken Wang | 1 | -22/+0 | |
| those register mask definitions are different in polaris compare to former gfx 8 gpus, so remove them from misusing. Signed-off-by: Ken Wang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2016-07-07 | drm/amdgpu/gfx80: Add QUICK_PG bit to GFX header and use it. | Tom St Denis | 1 | -2/+4 | |
| Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2016-05-04 | drm/amdgpu: add mmRLC_CGCG_CGLS_CTRL_3D & mmRLC_CGCG_RAMP_CTRL_3D | Flora Cui | 1 | -0/+2 | |
| Signed-off-by: Flora Cui <[email protected]> Reviewed-by: Jammy Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2016-03-17 | drm/amdgpu/gfx7: add MTYPE definition | Flora Cui | 1 | -0/+6 | |
| Signed-off-by: Flora Cui <[email protected]> Reviewed-by: Jammy Zhou <[email protected]> Reviewed-by: Alex Deucher <[email protected]> | |||||
| 2015-12-02 | drm/amd: add new gfx8 register definitions for EDC | Alex Deucher | 1 | -0/+13 | |
| EDC is a RAS feature for on chip memory. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2015-10-28 | drm/amdgpu: add GFX 8.1 register headers | Alex Deucher | 3 | -0/+30967 | |
| Minor differences compared to GFX 8.0 Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2015-06-03 | drm/amdgpu: add GCA 8.0 register headers | Alex Deucher | 3 | -0/+30445 | |
| These are register headers for the GCA (Graphics and Compute Array) block on the GPU. Acked-by: Christian König <[email protected]> Acked-by: Jammy Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2015-06-03 | drm/amdgpu: add GCA 7.2 register headers | Alex Deucher | 3 | -0/+27275 | |
| These are register headers for the GCA (Graphics and Compute Array) block on the GPU. Acked-by: Christian König <[email protected]> Acked-by: Jammy Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2015-06-03 | drm/amdgpu: add GCA 7.0 register headers | Alex Deucher | 1 | -0/+2532 | |
| These are register headers for the GCA (Graphics and Compute Array) block on the GPU. Acked-by: Christian König <[email protected]> Acked-by: Jammy Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||