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[WHY&HOW]
OTG has new functionality to allow P-State relative to VStartup. Keepout region
for this should be configured based on DML outputs same as other global sync
params.
Reviewed-by: Alvin Lee <[email protected]>
Signed-off-by: Jerry Zuo <[email protected]>
Signed-off-by: Dillon Varone <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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[WHAT & HOW]
We must wait for ODM double buffer updates to complete
before exiting the pipe update sequence or we may reduce
DISPCLK and hit some transient underflow (pixel rate is
reduced before the pipes have ODM enabled).
Reviewed-by: Samson Tam <[email protected]>
Cc: Mario Limonciello <[email protected]>
Cc: Alex Deucher <[email protected]>
Cc: [email protected]
Signed-off-by: Alex Hung <[email protected]>
Signed-off-by: Alvin Lee <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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why:
optc_401_set_drr was using an old optc3 function to update vtotal min and max,
causing crashes when disabling FAMS2
how:
Updated dcn401 to point to opt401 function for vtotal updates. This version of
the function has FAMS2 logic that allows for FAMS2 to be disabled.
Reviewed-by: Dillon Varone <[email protected]>
Acked-by: Zaeem Mohamed <[email protected]>
Signed-off-by: Relja Vojvodic <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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[WHY]
Currently 3-tap chroma subsampling is used for YCbCr422/420. When ODM
pipesplit is used, pixels on the left edge of ODM slices need one extra
pixel from the right edge of the previous slice to calculate the correct
chroma value.
Without this change, the chroma value is slightly different than
expected. This is usually imperceptible visually, but it impacts test
pattern CRCs for compliance test automation.
[HOW]
Update logic to use the register for adding extra left edge pixel for
YCbCr422/420 ODM cases.
Reviewed-by: George Shen <[email protected]>
Acked-by: Alex Hung <[email protected]>
Signed-off-by: Wenjing Liu <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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[why]
Switching between DSC clock or disable DSC block are not double buffered update.
Corruption is observed if these updates happen before DSC double buffered
disconnection.
[how]
Move DSC disable and refclk reset to post unlock update. Wait for DSC double buffered
disconnection and all mpccs are disconnected before reset DSC clock.
Reviewed-by: Samson Tam <[email protected]>
Acked-by: Tom Chung <[email protected]>
Signed-off-by: Wenjing Liu <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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[why]
When optc uses two pixel per container, each ODM slice width must be an
even number.
[how]
If ODM slice width is odd number increase it by 1.
Reviewed-by: Dillon Varone <[email protected]>
Acked-by: Wayne Lin <[email protected]>
Signed-off-by: Wenjing Liu <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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This commit fixes the kdoc for 'Enable CRTC' in `optc401_enable_crtc`
function.
Fixes the below with gcc W=1:
drivers/gpu/drm/amd/amdgpu/../display/dc/optc/dcn401/dcn401_optc.c:177: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* Enable CRTC
Fixes: 70839da63605 ("drm/amd/display: Add new DCN401 sources")
Cc: Rodrigo Siqueira <[email protected]>
Cc: Roman Li <[email protected]>
Cc: Qingqing Zhuo <[email protected]>
Cc: Aurabindo Pillai <[email protected]>
Cc: Tom Chung <[email protected]>
Signed-off-by: Srinivasan Shanmugam <[email protected]>
Reviewed-by: Tom Chung <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Add initial support for DCN 4.0.1.
Signed-off-by: Aurabindo Pillai <[email protected]>
Acked-by: Rodrigo Siqueira <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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