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path: root/drivers/crypto/hisilicon/zip
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2024-09-06crypto: hisilicon/qm - reset device before enabling itWeili Qian1-8/+15
Before the device is enabled again, the device may still store the previously processed data. If an error occurs in the previous task, the device may fail to be enabled again. Therefore, before enabling device, reset the device to restore the initial state. Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2024-09-06crypto: hisilicon - add a lock for the qp send operationChenghai Huang1-0/+3
Apply for a lock before the qp send operation to ensure no resource race in multi-concurrency situations. This modification has almost no impact on performance. Signed-off-by: Chenghai Huang <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2024-08-30crypto: hisilicon/zip - Optimize performance by replacing rw_lock with spinlockKuan-Wei Chiu1-7/+7
The req_lock is currently implemented as a rw_lock, but there are no instances where read_lock() is called. This means that the lock is effectively only used by writers, making it functionally equivalent to a simple spinlock. As stated in Documentation/locking/spinlocks.rst: "Reader-writer locks require more atomic memory operations than simple spinlocks. Unless the reader critical section is long, you are better off just using spinlocks." Since the rw_lock in this case incurs additional atomic memory operations without any benefit from reader-writer locking, it is more efficient to replace it with a spinlock. This patch implements that replacement to optimize the driver's performance. Signed-off-by: Kuan-Wei Chiu <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2024-06-07crypto: hisilicon/zip - optimize the address offset of the reg query functionChenghai Huang1-28/+20
Currently, the reg is queried based on the fixed address offset array. When the number of accelerator cores changes, the system can not flexibly respond to the change. Therefore, the reg to be queried is calculated based on the comp or decomp core base address. Signed-off-by: Chenghai Huang <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2024-04-12crypto: hisilicon - Adjust debugfs creation and release orderChenghai Huang1-13/+11
There is a scenario where the file directory is created but the file memory is not set. In this case, if a user accesses the file, an error occurs. So during the creation process of debugfs, memory should be allocated first before creating the directory. In the release process, the directory should be deleted first before releasing the memory to avoid the situation where the memory does not exist when accessing the directory. In addition, the directory released by the debugfs is a global variable. When the debugfs of an accelerator fails to be initialized, releasing the directory of the global variable affects the debugfs initialization of other accelerators. The debugfs root directory released by debugfs init should be a member of qm, not a global variable. Signed-off-by: Chenghai Huang <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2024-03-08crypto: hisilicon/zip - fix the missing CRYPTO_ALG_ASYNC in cra_flagsBarry Song1-0/+1
Add the missing CRYPTO_ALG_ASYNC flag since hisilizon zip driver works asynchronously. Cc: Zhou Wang <[email protected]> Signed-off-by: Barry Song <[email protected]> Acked-by: Yang Shen <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2024-01-26crypto: hisilicon - Fix smp_processor_id() warningsWenkai Lin1-1/+1
Switch to raw_smp_processor_id() to prevent a number of warnings from kernel debugging. We do not care about preemption here, as the CPU number is only used as a poor mans load balancing or device selection. If preemption happens during an encrypt/decrypt operation a small performance hit will occur but everything will continue to work, so just ignore it. This commit is similar to e7a9b05ca4 ("crypto: cavium - Fix smp_processor_id() warnings"). [ 7538.874350] BUG: using smp_processor_id() in preemptible [00000000] code: af_alg06/8438 [ 7538.874368] caller is debug_smp_processor_id+0x1c/0x28 [ 7538.874373] CPU: 50 PID: 8438 Comm: af_alg06 Kdump: loaded Not tainted 5.10.0.pc+ #18 [ 7538.874377] Call trace: [ 7538.874387] dump_backtrace+0x0/0x210 [ 7538.874389] show_stack+0x2c/0x38 [ 7538.874392] dump_stack+0x110/0x164 [ 7538.874394] check_preemption_disabled+0xf4/0x108 [ 7538.874396] debug_smp_processor_id+0x1c/0x28 [ 7538.874406] sec_create_qps+0x24/0xe8 [hisi_sec2] [ 7538.874408] sec_ctx_base_init+0x20/0x4d8 [hisi_sec2] [ 7538.874411] sec_aead_ctx_init+0x68/0x180 [hisi_sec2] [ 7538.874413] sec_aead_sha256_ctx_init+0x28/0x38 [hisi_sec2] [ 7538.874421] crypto_aead_init_tfm+0x54/0x68 [ 7538.874423] crypto_create_tfm_node+0x6c/0x110 [ 7538.874424] crypto_alloc_tfm_node+0x74/0x288 [ 7538.874426] crypto_alloc_aead+0x40/0x50 [ 7538.874431] aead_bind+0x50/0xd0 [ 7538.874433] alg_bind+0x94/0x148 [ 7538.874439] __sys_bind+0x98/0x118 [ 7538.874441] __arm64_sys_bind+0x28/0x38 [ 7538.874445] do_el0_svc+0x88/0x258 [ 7538.874447] el0_svc+0x1c/0x28 [ 7538.874449] el0_sync_handler+0x8c/0xb8 [ 7538.874452] el0_sync+0x148/0x180 Signed-off-by: Wenkai Lin <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2023-12-08crypto: hisilicon/zip - save capability registers in probe processZhiqi Song1-13/+60
Pre-store the valid value of the zip alg support related capability register in hisi_zip_qm_init(), which will be called by hisi_zip_probe(). It can reduce the number of capability register queries and avoid obtaining incorrect values in abnormal scenarios, such as reset failed and the memory space disabled. Fixes: db700974b69d ("crypto: hisilicon/zip - support zip capability") Signed-off-by: Zhiqi Song <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2023-12-08crypto: hisilicon/qm - add a function to set qm algsWenkai Lin1-41/+8
Extract a public function to set qm algs and remove the similar code for setting qm algs in each module. Signed-off-by: Wenkai Lin <[email protected]> Signed-off-by: Hao Fang <[email protected]> Signed-off-by: Zhiqi Song <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2023-12-01crypto: hisilicon/zip - add zip comp high perf mode configurationChenghai Huang1-0/+65
To meet specific application scenarios, the function of switching between the high performance mode and the high compression mode is added. Use the perf_mode=0/1 configuration to set the compression high perf mode, 0(default, high compression mode), 1(high performance mode). These two modes only apply to the compression direction and are compatible with software algorithm in both directions. Signed-off-by: Chenghai Huang <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2023-11-17crypto: hisilicon/qm - remove incorrect type castWeili Qian1-27/+27
The 'offset' type is unsigned long in 'struct debugfs_reg32', so type of values casts to unsigned long long is incorrect, and the values do not require type cast, remove them. Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2023-10-05crypto: hisilicon/qm - check function qp num before alg registerWeili Qian2-6/+32
When the Kunpeng accelerator executes tasks such as encryption and decryption have minimum requirements on the number of device queues. If the number of queues does not meet the requirement, the process initialization will fail. Therefore, the driver checks the number of queues on the device before registering the algorithm. If the number does not meet the requirements, the driver does not register the algorithm to crypto subsystem, the device is still added to the qm_list. Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2023-10-05crypto: hisilicon/qm - fix PF queue parameter issueLongfang Liu1-0/+5
If the queue isolation feature is enabled, the number of queues supported by the device changes. When PF is enabled using the current default number of queues, the default number of queues may be greater than the number supported by the device. As a result, the PF fails to be bound to the driver. After modification, if queue isolation feature is enabled, when the default queue parameter is greater than the number supported by the device, the number of enabled queues will be changed to the number supported by the device, so that the PF and driver can be properly bound. Fixes: 8bbecfb402f7 ("crypto: hisilicon/qm - add queue isolation support for Kunpeng930") Signed-off-by: Longfang Liu <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2023-09-20crypto: hisilicon/zip - remove zlib and gzipYang Shen2-288/+22
Remove the support of zlib-deflate and gzip. Signed-off-by: Yang Shen <[email protected]> Reviewed-by: Longfang Liu <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2023-09-20crypto: hisilicon/zip - support deflate algorithmYang Shen2-18/+72
Add the deflate algorithm support for hisilicon zip hardware. Signed-off-by: Yang Shen <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2023-03-17crypto: hisilicon/zip - remove unnecessary aer.h includeBjorn Helgaas1-1/+0
<linux/aer.h> is unused, so remove it. Signed-off-by: Bjorn Helgaas <[email protected]> Cc: Yang Shen <[email protected]> Cc: Zhou Wang <[email protected]> Cc: Nick Terrell <[email protected]> Acked-by: Longfang Liu <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2022-11-18crypto: hisilicon/qm - modify the process of regs dfxKai Ye1-4/+3
The last register logic and different register logic are combined. Use "u32" instead of 'int' in the regs function input parameter to simplify some checks. Signed-off-by: Kai Ye <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2022-09-16crypto: hisilicon - support get algs by the capability registerZhiqi Song1-5/+70
The value of qm algorithm can change dynamically according to the value of the capability register. Add xxx_set_qm_algs() function to obtain the algs that the hardware device supported from the capability register and set them into usr mode attribute files. Signed-off-by: Zhiqi Song <[email protected]> Signed-off-by: Wenkai Lin <[email protected]> Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2022-09-16crypto: hisilicon/zip - support zip capabilityWeili Qian3-42/+128
Add function 'hisi_zip_alg_support' to get device configuration information from capability registers, instead of determining whether to register an algorithm based on hardware platform's version. Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2022-09-16crypto: hisilicon/qm - get error type from hardware registersWeili Qian1-19/+55
Hardware V3 and later versions support get error type from registers. To be compatible with later hardware versions, get error type from registers instead of fixed marco. Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2022-09-16crypto: hisilicon/qm - get qp num and depth from hardware registersWeili Qian2-3/+4
Hardware V3 and later versions can obtain qp num and depth supported by the hardware from registers. To be compatible with later hardware versions, get qp num and depth from registers instead of fixed marcos. Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2022-09-16crypto: hisilicon/qm - get hardware features from hardware registersWeili Qian1-2/+2
Before hardware V3, hardwares do not provide the feature registers, driver resolves hardware differences based on the hardware version. As a result, the driver does not support the new hardware. Hardware V3 and later versions support to obtain hardware features, such as power-gating management and doorbell isolation, through the hardware registers. To be compatible with later hardware versions, the features of the current device is obtained by reading the hardware registers instead of the hardware version. Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2022-08-19crypto: hisilicon/zip - some misc cleanupYang Shen3-19/+23
Some cleanup for code: 1. Change names for easy to understand. 2. Unify the variables type. 3. Use the right return value. Signed-off-by: Yang Shen <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2022-08-19crypto: hisilicon/zip - optimization for performanceYang Shen1-14/+13
1.Remove some useless steps during doing requests. 2.Adjust the possibility of branch prediction. Signed-off-by: Yang Shen <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2022-08-19crypto: hisilicon/zip - fix mismatch in get/set sgl_sge_nrYe Weihua1-2/+2
KASAN reported this Bug: [17619.659757] BUG: KASAN: global-out-of-bounds in param_get_int+0x34/0x60 [17619.673193] Read of size 4 at addr fffff01332d7ed00 by task read_all/1507958 ... [17619.698934] The buggy address belongs to the variable: [17619.708371] sgl_sge_nr+0x0/0xffffffffffffa300 [hisi_zip] There is a mismatch in hisi_zip when get/set the variable sgl_sge_nr. The type of sgl_sge_nr is u16, and get/set sgl_sge_nr by param_get/set_int. Replacing param_get/set_int to param_get/set_ushort can fix this bug. Fixes: f081fda293ffb ("crypto: hisilicon - add sgl_sge_nr module param for zip") Signed-off-by: Ye Weihua <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2022-07-29crypto: hisilicon/zip - Use the bitmap API to allocate bitmapsChristophe JAILLET1-5/+5
Use bitmap_zalloc()/bitmap_free() instead of hand-writing them. It is less verbose and it improves the semantic. While at it, add an explicit include <linux/bitmap.h>. Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2022-06-17crypto: hisilicon/qm - move alloc qm->wq to qm.cWeili Qian1-16/+1
Before stopping the function, the driver needs to flush all the remaining work about event irq. Therefore, accelerator drivers use a private workqueue(qm->wq) to handle event irq instead of the system workqueue. This patch moves alloc workqueue from sec_main.c and zip_main.c to qm.c. Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2022-04-21crypto: hisilicon/qm - replace hisi_qm_release_qp() with hisi_qm_free_qps()Weili Qian1-1/+1
hisi_qm_free_qps() can release multiple queues in one call, and it is already exported. So, replace hisi_qm_release_qp() with hisi_qm_free_qps() in zip_crypto.c, and do not export hisi_qm_release_qp() outside qm.c. Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2022-04-15crypto: hisilicon/zip - support last word dumpingKai Ye1-1/+106
1. Add some debugging registers. 2. Add last word dumping function during zip engine controller reset. Signed-off-by: Kai Ye <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2022-04-15crypto: hisilicon/zip - support register checkingKai Ye1-8/+70
The value of the register is changed after the task running. A debugfs file node is added to help users to check the change of register values. Signed-off-by: Longfang Liu <[email protected]> Signed-off-by: Kai Ye <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2022-03-15hisi_acc_vfio_pci: Add helper to retrieve the struct pci_driverShameer Kolothum1-0/+6
struct pci_driver pointer is an input into the pci_iov_get_pf_drvdata(). Introduce helpers to retrieve the ACC PF dev struct pci_driver pointers as we use this in ACC vfio migration driver. Acked-by: Zhou Wang <[email protected]> Acked-by: Kai Ye <[email protected]> Acked-by: Longfang Liu <[email protected]> Signed-off-by: Shameer Kolothum <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Alex Williamson <[email protected]>
2022-03-15hisi_acc_qm: Move VF PCI device IDs to common headerShameer Kolothum1-6/+5
Move the PCI Device IDs of HiSilicon ACC VF devices to a common header and also use a uniform naming convention. This will be useful when we introduce the vfio PCI HiSilicon ACC live migration driver in subsequent patches. Cc: Bjorn Helgaas <[email protected]> Acked-by: Zhou Wang <[email protected]> Acked-by: Longfang Liu <[email protected]> Acked-by: Kai Ye <[email protected]> Signed-off-by: Shameer Kolothum <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> # pci_ids.h Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Alex Williamson <[email protected]>
2022-03-15crypto: hisilicon/qm: Move the QM header to include/linuxShameer Kolothum1-1/+1
Since we are going to introduce VFIO PCI HiSilicon ACC driver for live migration in subsequent patches, move the ACC QM header file to a common include dir. Acked-by: Zhou Wang <[email protected]> Acked-by: Longfang Liu <[email protected]> Acked-by: Kai Ye <[email protected]> Signed-off-by: Shameer Kolothum <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Alex Williamson <[email protected]>
2021-12-24crypto: hisilicon/zip - add new algorithms for uacce deviceYang Shen1-1/+4
Enable deflate/lz77_zstd algorithm for uacce device on Kunpeng930. Signed-off-by: Yang Shen <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-12-17crypto: hisilicon/zip - enable ssid for sva sglYang Shen1-1/+2
For Kunpeng 920, the bit 0 of register 'HZIP_SGL_RUSER_32_63' stand for whether the ssid is valid. So this bit should be set as valid for sva mode. Signed-off-by: Yang Shen <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-11-26crypto: hisilicon - modify the value of engine type rateKai Ye1-2/+2
Modify the value of type rate from new QM spec. Signed-off-by: Kai Ye <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-10-01crypto: hisilicon/zip - Fix spelling mistake "COMSUMED" -> "CONSUMED"Colin Ian King1-1/+1
There is a spelling mistake in a literal string. Fix it. Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-08-21crypto: hisilicon - change parameter passing of debugfs functionWeili Qian1-7/+4
To avoid repeatedly obtaining 'qm' from 'filp', parameter passing of debugfs function directly use 'qm' instead of 'filp'. Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-08-21crypto: hisilicon - support runtime PM for accelerator deviceWeili Qian1-4/+30
Add runtime PM support for Kunpeng930 accelerator device. Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-08-21crypto: hisilicon - using 'debugfs_create_file' instead of ↵Weili Qian1-1/+11
'debugfs_create_regset32' The accelerator devices support runtime PM, when device is in suspended, an exception will occur if reading registers. Therefore, this patch uses 'debugfs_create_file' instead of 'debugfs_create_regset32' to create debugfs file, and then the driver can get the device status before reading the register. Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-08-12crypto: hisilicon - enable zip device clock gatingWeili Qian1-0/+26
Kunpeng930 zip device supports dynamic clock gating. When executing tasks, the algorithm core is opened, and when idle, the algorithm core is closed. This patch enables zip dynamic clock gating by writing hardware registers. Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-06-17crypto: hisilicon/zip - adds the max shaper type rateKai Ye1-0/+11
The ZIP driver support configure each function's QoS in the Host for Kunpeng930. The ZIP driver needs to configure the maximum shaper type rate. Signed-off-by: Kai Ye <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-05-28crypto: hisilicon/qm - support address prefetchingLongfang Liu1-0/+50
Kunpeng930 hardware supports address prefetching to improve performance before doing tasks in SVA scenario. This patch enables this function in device initialization by writing hardware registers. In the process of reset, address prefetching is disabled to avoid the failure of interaction between accelerator device and SMMU. Signed-off-by: Longfang Liu <[email protected]> Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-05-23crypto: hisilicon/qm - enable to close master ooo when NFE occursWeili Qian1-12/+24
Kunpeng930 could be able to close master ooo when NFE occurs, which will disable memory accessing from device and execute tasks. This ensures that errors do not spread. This patch enables the hardware to close master ooo when an error occurs by writing hardware registers, and ensures that the driver will not drain qp because the hardware will empty the tasks automatically. Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-05-23crypto: hisilicon/qm - adjust order of device error configurationWeili Qian1-3/+3
In order to avoid reporting an exception but the error type is not configured, the driver needs to configure the error type first, and then enable the error interrupt. Before executing the task, hardware error initialization is needed so that the hardware can detect the error in time. Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-04-22crypto: hisilicon - support new error types for ZIPWeili Qian1-2/+7
Kunpeng930 ZIP adds 'zip_axi_poison_err' 'zip_sva_err' and 'QM_ACC_DO_TASK_TIMEOUT' hardware error types. This patch enables the error types and configures the error types as NFE. Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-04-22crypto: hisilicon - dynamic configuration 'err_info'Weili Qian1-10/+15
'err_info' does not support dynamic configuration since it is const type. Therefore, in order to support new error type later, 'err_info' is changed to dynamic configuration. Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-04-02crypto: hisilicon/zip - support new 'sqe' type in Kunpeng930Yang Shen2-0/+26
The Kunpeng930 changes some field meanings in 'sqe'. So add a new 'hisi_zip_sqe_ops' to describe the 'sqe' operations. Signed-off-by: Yang Shen <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-04-02crypto: hisilicon/zip - initialize operations about 'sqe' in 'acomp_alg.init'Yang Shen1-31/+110
The operations about 'sqe' are different on some hardwares. Add a struct 'hisi_zip_sqe_ops' to describe the operations in a hardware. And choose the 'ops' in 'hisi_zip_acomp_init' according to the hardware. Signed-off-by: Yang Shen <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-04-02crypto: hisilicon/zip - add comments for 'hisi_zip_sqe'Yang Shen2-15/+34
Some fields of 'hisi_zip_sqe' are unused, and some fields have misc utilities. So add comments for used fields and make others unnamed. Signed-off-by: Yang Shen <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
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