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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2018-03-12clk: hisilicon: add hisi phase clock supporttianshuliang4-1/+165
2018-03-11clk: update cached phase to respect the fact when setting phaseShawn Lin1-1/+4
2018-03-11clk: stm32mp1: add Debug clocksGabriel Fernandez1-0/+22
2018-03-11clk: stm32mp1: add MCO clocksGabriel Fernandez1-0/+20
2018-03-11clk: stm32mp1: add RTC clockGabriel Fernandez1-0/+15
2018-03-11clk: stm32mp1: add Peripheral & Kernel ClocksGabriel Fernandez1-27/+820
2018-03-11clk: stm32mp1: add Kernel timersGabriel Fernandez1-0/+185
2018-03-11clk: stm32mp1: add Sub System clocksGabriel Fernandez1-0/+85
2018-03-11clk: stm32mp1: add Post-dividers for PLLGabriel Fernandez1-0/+221
2018-03-11clk: stm32mp1: add PLL clocksGabriel Fernandez1-0/+209
2018-03-11clk: stm32mp1: add Source Clocks for PLLsGabriel Fernandez1-0/+60
2018-03-11clk: stm32mp1: add MP1 gate for hse/hsi/csi oscillatorsGabriel Fernandez1-0/+143
2018-03-11clk: stm32mp1: Introduce STM32MP1 clock driverGabriel Fernandez3-0/+371
2018-03-08clk: tegra: MBIST work around for Tegra210Peter De Schrijver1-2/+342
2018-03-08clk: tegra: add fence_delay for clock registersPeter De Schrijver1-0/+7
2018-03-08clk: tegra: Add la clock for Tegra210Peter De Schrijver1-0/+14
2018-03-08clk: ti: am43xx: add set-rate-parent support for display clkctrl clockTero Kristo1-1/+1
2018-03-08clk: ti: clkctrl: add support for CLK_SET_RATE_PARENT flagTero Kristo1-0/+2
2018-03-08clk: ti: am33xx: add set-rate-parent support for display clkctrl clockTero Kristo1-1/+1
2018-03-08clk: keystone: sci-clk: add support for dynamically probing clocksTero Kristo1-290/+90
2018-03-08clk: ti: add support for clock latching to mux clocksTero Kristo2-3/+11
2018-03-08clk: ti: add support for clock latching to divider clocksTero Kristo2-6/+21
2018-03-08clk: ti: add generic support for clock latchingTero Kristo2-0/+16
2018-03-08clk: ti: add support for register read-modify-write low-level operationTero Kristo1-0/+24
2018-03-06clk: samsung: exynos5250: Move PD-dependent clocks to Exynos5 sub-CMUMarek Szyprowski3-16/+37
2018-03-06clk: samsung: exynos5420: Move PD-dependent clocks to Exynos5 sub-CMUMarek Szyprowski3-26/+98
2018-03-06clk: samsung: Add Exynos5 sub-CMU clock driverMarek Szyprowski2-0/+212
2018-03-05clk: rockchip: Prevent calculating mmc phase if clock rate is zeroShawn Lin1-0/+23
2018-03-02clk: rockchip: Free the memory on the error pathShawn Lin1-4/+18
2018-03-02clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEOJernej Skrabec1-1/+3
2018-03-02clk: sunxi-ng: h3: h5: Allow some clocks to set parent rateJernej Skrabec1-3/+6
2018-03-02clk: sunxi-ng: h3: h5: Add minimal rate for video PLLJernej Skrabec1-11/+12
2018-03-02clk: sunxi-ng: Add check for minimal rate to NM PLLsJernej Skrabec2-0/+34
2018-03-01clk: imx: imx7d: correct video pll clock treeAnson Huang1-40/+44
2018-02-28clk: add support for clocks provided by SCMISudeep Holla3-0/+213
2018-02-28clk: imx: imx7d: add the Keypad Port module clockStefan Agner1-0/+1
2018-02-28clk: imx7d: add CAAM clockRui Miguel Silva1-0/+1
2018-02-27clk: hi3798cv200: add COMBPHY0 clock supportJianguo Sun1-4/+11
2018-02-27clk: hi3798cv200: fix define indentationShawn Guo1-24/+24
2018-02-27clk: hi3798cv200: add support for HISTB_USB2_OTG_UTMI_CLKShawn Guo1-0/+2
2018-02-27clk: hi3798cv200: correct IR clock parentYounian Wang1-1/+1
2018-02-27clk: hi3798cv200: fix unregister call sequence in error pathShawn Guo1-7/+6
2018-02-26clk: renesas: cpg-mssr: Add support for R-Car M3-NJacopo Mondi5-0/+347
2018-02-23clk: samsung: Add compile time PLL rate validatorsAndrzej Hajda10-344/+372
2018-02-23clk: samsung: s3c2410: Fix PLL ratesAndrzej Hajda1-8/+8
2018-02-23clk: samsung: exynos7: Fix PLL ratesAndrzej Hajda1-1/+1
2018-02-23clk: samsung: exynos5433: Fix PLL ratesAndrzej Hajda1-6/+6
2018-02-23clk: samsung: exynos5260: Fix PLL ratesAndrzej Hajda1-1/+1
2018-02-23clk: samsung: exynos5250: Fix PLL ratesAndrzej Hajda1-4/+4
2018-02-23clk: samsung: exynos3250: Fix PLL ratesAndrzej Hajda1-2/+2