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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2018-03-20clk: davinci: Add platform information for TI DM355 PLLDavid Lechner4-0/+85
2018-03-20clk: davinci: Add platform information for TI DA850 PLLDavid Lechner4-0/+222
2018-03-20clk: davinci: Add platform information for TI DA830 PLLDavid Lechner4-0/+76
2018-03-20clk: davinci: New driver for davinci PLL clocksDavid Lechner4-0/+1014
2018-03-20clk: scmi: use devm_of_clk_add_hw_provider() API and drop scmi_clocks_removeSudeep Holla1-10/+2
2018-03-20clk: mediatek: add audsys support for MT2701Ryder Lee3-0/+193
2018-03-20clk: mediatek: add devm_of_platform_populate() for MT7622 audsysRyder Lee1-1/+13
2018-03-19clk: qcom: Add support for controlling Fabia PLLAmit Nischal2-8/+311
2018-03-19clk: qcom: Clear hardware clock control bit of RCGAmit Nischal1-2/+3
2018-03-19clk: qcom: rpmcc: Add support to XO buffered clocksSrinivas Kandagatla1-1/+78
2018-03-19clk: mediatek: update clock driver of MT2712Weiyi Lu1-14/+55
2018-03-19clk: lpc32xx: Set name of regmap_configJeffy Chen1-0/+1
2018-03-19clk: Don't show the incorrect clock phaseShawn Lin1-0/+3
2018-03-19clk: mvebu: armada-38x: add support for missing clocksRichard Genoud1-7/+7
2018-03-19clk: clk-gpio: Allow GPIO to sleep in set/get_parentMike Looijmans1-2/+2
2018-03-19clk: enable hi655x common clk automaticallyRiku Voipio1-2/+4
2018-03-19clk: stm32: add configuration flags for each of the stm32 driversBenjamin Gaignard2-2/+16
2018-03-19clk: stm32: Add clk entry for SDMMC2 on stm32F769Patrice Chotard1-1/+2
2018-03-19clk: stm32: Add DSI clock for STM32F469 BoardGabriel Fernandez1-1/+10
2018-03-19clk: uniphier: add Pro4/Pro5/PXs2 audio system clockKatsuhiro Suzuki1-0/+11
2018-03-19clk: mediatek: update missing clock data for MT7622 audsysRyder Lee1-0/+1
2018-03-19clk: mediatek: fix PWM clock source by adding a fixed-factor clockSean Wang1-7/+8
2018-03-19clk: mvebu: cp110: Fix clock tree representationGregory CLEMENT1-55/+39
2018-03-19clk: Re-use DEFINE_SHOW_ATTRIBUTE() macroAndy Shevchenko1-53/+7
2018-03-19clk: bcm2835: Protect sections updating shared registersBoris Brezillon1-0/+4
2018-03-19clk: bcm2835: Fix ana->maskX definitionsBoris Brezillon1-4/+4
2018-03-18clk: sunxi-ng: add support for the Allwinner H6 CCUIcenowy Zheng4-0/+1269
2018-03-18clk: sunxi-ng: Support fixed post-dividers on NKMP style clocksIcenowy Zheng2-3/+19
2018-03-16clk: Print the clock name and warning causeFabio Estevam1-7/+12
2018-03-16clk: hisilicon: mark wdt_mux_p[] as constArnd Bergmann1-1/+1
2018-03-16clk: fix false-positive Wmaybe-uninitialized warningArnd Bergmann1-3/+3
2018-03-16clk: sprd: add RTC gate for SC9860Chunyan Zhang1-0/+76
2018-03-16clk: qcom: smd-rpm: Migrate to devm_of_clk_add_hw_provider()Stephen Boyd1-8/+1
2018-03-16clk: imx: pllv2: avoid using uninitialized valuesLucas Stach1-1/+5
2018-03-16clk: qcom: gcc-msm8996: Mark aggre0 noc clks as criticalSrinivas Kandagatla1-4/+4
2018-03-16clk: versatile: Remove WARNs in ->round_rate()Brian Starkey1-2/+2
2018-03-16clk: versatile: add min/max rate boundaries for vexpress osc clockSudeep Holla1-0/+1
2018-03-16clk: samsung: Mark a few things staticStephen Boyd3-46/+46
2018-03-15clk: samsung: Add fout=196608001 Hz EPLL rate entry for exynos4412Sylwester Nawrocki1-0/+1
2018-03-15clk: aspeed: Prevent reset if clock is enabledEddie James1-12/+17
2018-03-15clk: aspeed: Fix is_enabled for certain clocksEddie James1-1/+2
2018-03-14clk: meson: Drop unused local variable and add staticStephen Boyd3-11/+10
2018-03-14Merge tag 'clk-imx-4.17-misc' of git://git.kernel.org/pub/scm/linux/kernel/gi...Stephen Boyd3-48/+55
2018-03-14clk: hisilicon: Mark phase_ops staticStephen Boyd1-1/+1
2018-03-14clk: samsung: exynos5250: Add missing clocks for FIMC LITE SYSMMU devicesMarek Szyprowski1-0/+6
2018-03-14clk: rockchip: Add 1.6GHz PLL rate for rk3399Derek Basehore1-0/+1
2018-03-13clk: renesas: r8a77965: Replace DU2 clockJacopo Mondi1-1/+1
2018-03-13clk: rockchip: Restore the clock phase after the rate was changedShawn Lin1-1/+38
2018-03-13clk: meson: clean-up clk81 clocksJerome Brunet2-8/+4
2018-03-13clk: meson: add fdiv clock gatesJerome Brunet6-33/+278