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2024-08-14arm64: dts: qcom: add generic compat string to RPM glink channelsDmitry Baryshkov1-1/+1
Add the generic qcom,smd-rpm / qcom,glink-smd-rpm compatible to RPM nodes to follow the schema. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20240729-fix-smd-rpm-v2-5-0776408a94c5@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-06arm64: dts: qcom: ipq6018: Disable SS instance in Parkmode for USBKrishna Kurapati1-0/+1
For Gen-1 targets like IPQ6018, it is seen that stressing out the controller in host mode results in HC died error: xhci-hcd.12.auto: xHCI host not responding to stop endpoint command xhci-hcd.12.auto: xHCI host controller not responding, assume dead xhci-hcd.12.auto: HC died; cleaning up And at this instant only restarting the host mode fixes it. Disable SuperSpeed instance in park mode for IPQ6018 to mitigate this issue. Cc: stable@vger.kernel.org Fixes: 20bb9e3dd2e4 ("arm64: dts: qcom: ipq6018: add usb3 DT description") Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240704152848.3380602-2-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-25arm64: dts: qcom: ipq6018: add sdhci nodeChukun Pan1-0/+19
Add node to support mmc controller inside of IPQ6018. This controller supports both eMMC and SD cards. Tested with: eMMC (HS200) SD Card (SDR50/SDR104) Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://lore.kernel.org/r/20240620150122.1406631-3-amadeus@jmu.edu.cn Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-07arm64: dts: qcom: ipq6018-*: Remove thermal zone polling delaysKonrad Dybcio1-6/+0
All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-1-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-01arm64: dts: qcom: ipq6018: fix GCC node nameDmitry Baryshkov1-1/+1
Device nodes should have generic names. Use 'clock-controller@' as a GCC node name instead of a non-generic 'gcc@'. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-13-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: ipq6018: Add PCIe bridge nodeManivannan Sadhasivam1-0/+10
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-16-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-01Merge tag 'qcom-arm64-for-6.9' of ↵Arnd Bergmann1-0/+159
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt Qualcomm ARM64 DeviceTree updates for v6.9 Four variants of Samsung Galaxy Core Prime and Grand Prime, built on MSM8916, and the Hardware Development Kit (HDK) for SM8550, are introduced. On X Elite audio and compute remoteprocs, IPCC, PCIe, AOSS QMP, SMP2P, TCSR, USB, display, audio, and soundwire support is introduced, and enabled across the CRD and QCP devices. For SM8650 PCIe controllers are moved to GIC-ITS and msi-map-mask is defined. Missing qlink-logging reserved-memory region is added for the modem remoteproc. FastRPC compute contexts are marked dma-coherent. Audio, USB Type-C and PM8010 support is introduced across MTP and QRD devices. GPU cooling devices are hooked up across MSM8916, MSM8939, SC8180X, SDM630, SDM845, SM6115, SM8150, SM8250, SM8350, and SM8550. UFS PHY clocks are corrected across MSM8996, MSM8998, SC8180X, SC8280XP, SDM845, SM6115, SM6125, SM8150, SM8250, SM8350, SM8550, and SM8650. PCI MSI interrupts are wired up across SM8150, SM8250, SM8350, SM8450, SM8550, SM8650, SC7280, and SC8180X On IPQ6018 QUP5 I2C, tsens sand thermal zones are defined. The Inline Crypto Engine (ICE) is enabled for IPQ9574. On MSM8953 the GPU and its IOMMU is introduced, the reset for the display subsystem is also wired up. VLS CLAMP registers are specified for USB3 PHYs on MSM8998, QCM2290, and SM6115. USB Type-C port management is enabled on QRB4210 RB2. On the SA8295P ADP the MAX20411 regulator powering the GPU rails is introduced and the GPU is enabled. The first PCI instance on SA8540P Ride is disabled for now, as a fix for the interrupt storm produced here has not been presented. On SA8775P the firmware memory map has changed and is updated. Safety IRQ is added to the Ethernet controller. On SC7180 UFS support is introduced and the cros-ec-spi is marked as wakeup source. For SC7280 capacity and DPC properties are added, cryptobam definition is improved to work in more firmware environments, more Chrome-specific properties are moved out from main dtsi, and cros-ec-spi is maked as a wakeup source. Slimbus definition is added to the platform. A missing reserved-memory range is added to Fairphone FP5, PMIC GLINK and Venus are enabled. LEDs are introduced and voltage settings corrected on the QCM6490 IDP, and RB3gen2 sees the same voltage changes and GCC protected clocks are introduced to make the board boot properly. RPMh sleep stats and a variety of cleanups and fixes are introduced for SC8180X. On SC8280XP the additional tsens instances are introduced. Camera Subsystem and Camera Control Interface (CCI) are added. PMIC die-temp vadc channels are introduced on the CRD, to allow ADC channels to be tied to the shared PMIC temp-alarms, to actually report temperature. On SDM630 USB QMP PHY support is introduced and enabled on the Inforce IFC6560 board. On the various Sony Xperia XA2 variants WLED is enabled and configured. On SM6350 display subsystem interconnects and tsens-based thermal zones are added. On SM7125 UFS support is added. On Fairphone FP4, on SM7225, display and GPU are enabled, and firmware paths are corrected. SM8150 PCIe controller definitions are corrected. As with SM8650, the SM8550 the fastrpc compute contexts are marked dm-coherent, and PCIe controllers are moved to use GIC-ITS. The UFS controller frequency definition is moved to the generic opp-table. Touchscreen is enabled on the QRD device. As usual, a variety of smaller cleanups and corrections to match DeviceTree bindings and style guidelines are introduced across the various files. * tag 'qcom-arm64-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (176 commits) arm64: dts: qcom: sm6115: fix USB PHY configuration arm64: dts: sm8650: Add msi-map-mask for PCIe nodes arm64: dts: qcom: replace underscores in node names dt-bindings: arm: qcom: Add Samsung Galaxy Tab 4 10.1 LTE arm64: dts: qcom: pm4125: define USB-C related blocks arm64: dts: qcom: sa8540p-ride: disable pcie2a node arm64: dts: qcom: sc7280: add slimbus DT node arm64: dts: qcom: sc7280: Add capacity and DPC properties arm64: dts: qcom: pmi632: Add PBS client and use in LPG node arm64: dts: qcom: sm8550: Use GIC-ITS for PCIe0 and PCIe1 arm64: dts: qcom: sm8150: correct PCIe wake-gpios arm64: dts: qcom: sdm845-db845c: correct PCIe wake-gpios arm64: dts: qcom: sm7225-fairphone-fp4: Enable display and GPU arm64: dts: qcom: sm6350: Remove "disabled" state of GMU arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add fuel gauge arm64: dts: qcom: sm6350: Add interconnect for MDSS arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add initial device trees arm64: dts: qcom: sm8550: Switch UFS from opp-table-hz to opp-v2 arm64: dts: qcom: sc8180x: describe all PCI MSI interrupts arm64: dts: qcom: minor whitespace cleanup ... Link: https://lore.kernel.org/r/20240225050146.484422-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-02-20arm64: dts: qcom: Fix interrupt-map cell sizesRob Herring1-4/+4
The PCI node interrupt-map properties have the wrong size as #address-cells in the interrupt parent are not accounted for. The dtc interrupt_map check catches this, but the warning is off because its dependency, interrupt_provider, is off by default. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240213-arm-dt-cleanups-v1-5-f2dee1292525@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-02-06arm64: dts: qcom: ipq6018: add thermal zonesMantas Pucka1-0/+121
Add thermal zones to make use of thermal sensors data. For CPU zone, add cooling device that uses CPU frequency scaling. Signed-off-by: Mantas Pucka <mantas@8devices.com> Link: https://lore.kernel.org/r/1706173452-1017-4-git-send-email-mantas@8devices.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: ipq6018: add tsens nodeMantas Pucka1-0/+10
IPQ6018 has temperature sensing HW block compatible with IPQ8074. Add node for it. Signed-off-by: Mantas Pucka <mantas@8devices.com> Link: https://lore.kernel.org/r/1706173452-1017-3-git-send-email-mantas@8devices.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: ipq6018: add QUP5 I2C nodeIsaev Ruslan1-0/+15
Add node to support this bus inside of IPQ6018. For example, this bus is used to work with the voltage regulator (mp5496) on the Yuncore AX840 wireless AP. Signed-off-by: Isaev Ruslan <legale.legale@gmail.com> Link: https://lore.kernel.org/r/CACDmYyfOe-jcgj4BAD8=pr08sHpOF=+FRcwrouuLAVsa4+zwtw@mail.gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: Fix hs_phy_irq for QUSB2 targetsKrishna Kurapati1-0/+13
On several QUSB2 Targets, the hs_phy_irq mentioned is actually qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq to qusb2_phy for such targets. In actuality, the hs_phy_irq is also present in these targets, but kept in for debug purposes in hw test environments. This is not triggered by default and its functionality is mutually exclusive to that of qusb2_phy interrupt. Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets. Add missing ss_phy_irq on some targets which allows for remote wakeup to work on a Super Speed link. Also modify order of interrupts in accordance to bindings update. Since driver looks up for interrupts by name and not by index, it is safe to modify order of these interrupts in the DT. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Link: https://lore.kernel.org/r/20240125185921.5062-2-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19arm64: dts: qcom: ipq6018: fix clock rates for GCC_USB0_MOCK_UTMI_CLKChukun Pan1-1/+1
The downstream QSDK kernel [1] and GCC_USB1_MOCK_UTMI_CLK are both 24MHz. Adjust GCC_USB0_MOCK_UTMI_CLK to 24MHz to avoid the following error: clk: couldn't set gcc_usb0_mock_utmi_clk clk rate to 20000000 (-22), current rate: 24000000 1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/486c8485f59 Fixes: 5726079cd486 ("arm64: dts: ipq6018: Use reference clock to set dwc3 period") Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://lore.kernel.org/r/20231218150805.1228160-1-amadeus@jmu.edu.cn Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: Use "pcie" as the node name instead of "pci"Manivannan Sadhasivam1-1/+1
Qcom SoCs doesn't support the legacy PCI, but only PCIe. So use the correct node name for the controller instances. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20231206135540.17068-3-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: ipq6018: Add QUP5 SPI nodeChukun Pan1-0/+14
Add node to support the QUP5 SPI controller inside of IPQ6018. Some routers use this bus to connect SPI TPM chips. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://lore.kernel.org/r/20231203154003.532765-1-amadeus@jmu.edu.cn Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: ipq6018: Add remaining QUP UART nodeChukun Pan1-0/+50
Add node to support all the QUP UART node controller inside of IPQ6018. Some routers use these bus to connect Bluetooth chips. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://lore.kernel.org/r/20231203153914.532654-1-amadeus@jmu.edu.cn Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-02arm64: dts: qcom: ipq6018: use CPUFreq NVMEMRobert Marko1-1/+13
IPQ6018 comes in multiple SKU-s and some of them dont support all of the OPP-s that are current set, so lets utilize CPUFreq NVMEM to allow only supported OPP-s based on the SoC dynamically. As an example, IPQ6018 is generaly rated at 1.8GHz but some silicon only goes up to 1.5GHz and is marked as such via an eFuse. Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231021120048.231239-1-robimarko@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-11-14arm64: dts: qcom: ipq6018: switch USB QMP PHY to new style of bindingsDmitry Baryshkov1-20/+15
Change the USB QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230824211952.1397699-8-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-10-21arm64: dts: qcom: ipq6018: include the GPLL0 as clock provider for mailboxKathiravan Thirumoorthy1-2/+2
While the kernel is booting up, APSS clock / CPU clock will be running at 800MHz with GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be configured to the rate based on the opp table and the source also will be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0, with this inclusion, CPU Freq correctly reports that CPU is running at 800MHz rather than 24MHz. Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-9-c8ceb1a37680@quicinc.com [bjorn: Updated commit message, as requested by Kathiravan] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-19arm64: dts: qcom: ipq6018: Fix tcsr_mutex register sizeVignesh Viswanathan1-1/+1
IPQ6018's TCSR Mutex HW lock register has 32 locks of size 4KB each. Total size of the TCSR Mutex registers is 128KB. Fix size of the tcsr_mutex hwlock register to 0x20000. Changes in v2: - Drop change to remove qcom,ipq6018-tcsr-mutex compatible string - Added Fixes and stable tags Cc: stable@vger.kernel.org Fixes: 5bf635621245 ("arm64: dts: ipq6018: Add a few device nodes") Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230905095535.1263113-2-quic_viswanat@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-19arm64: dts: qcom: ipq6018: Fix hwlock index for SMEMVignesh Viswanathan1-1/+1
SMEM uses lock index 3 of the TCSR Mutex hwlock for allocations in SMEM region shared by the Host and FW. Fix the SMEM hwlock index to 3 for IPQ6018. Cc: stable@vger.kernel.org Fixes: 5bf635621245 ("arm64: dts: ipq6018: Add a few device nodes") Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230904172516.479866-3-quic_viswanat@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-19arm64: dts: qcom: ipq6018: switch PCIe QMP PHY to new style of bindingsDmitry Baryshkov1-20/+12
Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230820142035.89903-9-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-13arm64: dts: qcom: Add rpm-proc node for GLINK gplatformsStephan Gerhold1-22/+26
Rather than having the RPM GLINK channels as the only child of a dummy top-level rpm-glink node, switch to representing the RPM as remoteproc like all the other remoteprocs (modem DSP, ...). This allows assigning additional subdevices to it like the MPM interrupt-controller or rpm-master-stats. Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # SM6375 Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-11-a07dcdefd918@gerhold.net Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-06-29Merge tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-8/+24
Pull ARM SoC devicetree updates from Arnd Bergmann: "The biggest change this time is for the 32-bit devicetree files, which are all moved to a new location, using separate subdirectories for each SoC vendor, following the same scheme that is used on arm64, mips and riscv. This has been discussed for many years, but so far we never did this as there was a plan to move the files out of the kernel entirely, which has never happened. The impact of this will be that all external patches no longer apply, and anything depending on the location of the dtb files in the build directory will have to change. The installed files after 'make dtbs_install' keep the current location. There are six added SoCs here that are largely variants of previously added chips. Two other chips are added in a separate branch along with their device drivers. - The Samsung Exynos 4212 makes its return after the Samsung Galaxy Express phone is addded at last. The SoC support was originally added in 2012 but removed again in 2017 as it was unused at the time. - Amlogic C3 is a Cortex-A35 based smart IP camera chip - Qualcomm MSM8939 (Snapdragon 615) is a more featureful variant of the still common MSM8916 (Snapdragon 410) phone chip that has been supported for a long time. - Qualcomm SC8180x (Snapdragon 8cx) is one of their earlier high-end laptop chips, used in the Lenovo Flex 5G, which is added along with the reference board. - Qualcomm SDX75 is the latest generation modem chip that is used as a peripherial in phones but can also run a standalone Linux. Unlike the prior 32-bit SDX65 and SDX55, this now has a 64-bit Cortex-A55. - Alibaba T-Head TH1520 is a quad-core RISC-V chip based on the Xuantie C910 core, a step up from all previously added rv64 chips. All of the above come with reference board implementations, those included there are 39 new board files, but only five more 32-bit this time, probably a new low: - Marantec Maveo board based on dhcor imx6ull module - Endian 4i Edge 200, based on the armv5 Marvell Kirkwood chip - Epson Moverio BT-200 AR glasses based on TI OMAP4 - PHYTEC STM32MP1-3 Dev board based on STM32MP15 PHYTEC SOM - ICnova ADB4006 board based on Allwinner A20 On the 64-bit side, there are also fewer addded machines than we had in the recent releases: - Three boards based on NXP i.MX8: Emtop SoM & Baseboard, NXP i.MX8MM EVKB board and i.MX8MP based Gateworks Venice gw7905-2x device. - NVIDIA IGX Orin and Jetson Orin Nano boards, both based on tegra234 - Qualcomm gains support for 6 reference boards on various members of their IPQ networking SoC series, as well as the Sony Xperia M4 Aqua phone, the Acer Aspire 1 laptop, and the Fxtec Pro1X board on top of the various reference platforms for their new chips. - Rockchips support for several newer boards: Indiedroid Nova (rk3588), Edgeble Neural Compute Module 6B (rk3588), FriendlyARM NanoPi R2C Plus (rk3328), Anbernic RG353PS (rk3566), Lunzn Fastrhino R66S/R68S (rk3568) - TI K3/AM625 based PHYTEC phyBOARD-Lyra-AM625 board and Toradex Verdin family with AM62 COM, carrier and dev boards Other changes to existing boards contain the usual minor improvements along with - continued updates to clean up dts files based on dtc warnings and binding checks, in particular cache properties and node names - support for devicetree overlays on at91, bcm283x - significant additions to existing SoC support on mediatek, qualcomm, ti k3 family, starfive jh71xx, NXP i.MX6 and i.MX8, ST STM32MP1 As usual, a lot more detail is available in the individual merge commits" * tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (926 commits) ARM: mvebu: fix unit address on armada-390-db flash ARM: dts: Move .dts files to vendor sub-directories kbuild: Support flat DTBs install ARM: dts: Add .dts files missing from the build ARM: dts: allwinner: Use quoted #include ARM: dts: lan966x: kontron-d10: add PHY interrupts ARM: dts: lan966x: kontron-d10: fix SPI CS ARM: dts: lan966x: kontron-d10: fix board reset ARM: dts: at91: Enable device-tree overlay support for AT91 boards arm: dts: Enable device-tree overlay support for AT91 boards arm64: dts: exynos: Remove clock from Exynos850 pmu_system_controller ARM: dts: at91: use generic name for shutdown controller ARM: dts: BCM5301X: Add cells sizes to PCIe nodes dt-bindings: firmware: brcm,kona-smc: convert to YAML riscv: dts: sort makefile entries by directory riscv: defconfig: enable T-HEAD SoC MAINTAINERS: add entry for T-HEAD RISC-V SoC riscv: dts: thead: add sipeed Lichee Pi 4A board device tree riscv: dts: add initial T-HEAD TH1520 SoC device tree riscv: Add the T-HEAD SoC family Kconfig option ...
2023-05-26arm64: dts: qcom: ipq6018: drop incorrect SPI bus spi-max-frequencyKrzysztof Kozlowski1-2/+0
The spi-max-frequency property belongs to SPI devices, not SPI controller: ipq6018-cp01-c1.dtb: spi@78b5000: Unevaluated properties are not allowed ('spi-max-frequency' was unexpected) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230416123730.300863-1-krzysztof.kozlowski@linaro.org
2023-05-26arm64: dts: qcom: add few more reserved memory regionVignesh Viswanathan1-3/+13
In IPQ SoCs, bootloader will collect the system RAM contents upon crash for the post morterm analysis. If we don't reserve the memory region used by bootloader, obviously linux will consume it and upon next boot on crash, bootloader will be loaded in the same region, which will lead to loose some of the data, sometimes we may miss out critical information. So lets reserve the region used by the bootloader. Similarly SBL copies some data into the reserved region and it will be used in the crash scenario. So reserve 1MB for SBL as well. While at it, drop the size padding in the reserved memory region, wherever applicable. Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526110653.27777-4-quic_viswanat@quicinc.com
2023-05-26arm64: dts: qcom: enable the download mode supportVignesh Viswanathan1-0/+1
Like any other Qualcomm SoCs, IPQ8074 and IPQ6018 also supports the download mode to collect the RAM dumps if system crashes, to perform the post mortem analysis. Add support for the same. Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526110653.27777-3-quic_viswanat@quicinc.com
2023-05-26arm64: dts: qcom: ipq6018: add QFPROM nodeKathiravan T1-0/+7
IPQ6018 has efuse region to determine the various HW quirks. Lets add the initial support and the individual fuses will be added as they are required. Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526125305.19626-4-quic_kathirav@quicinc.com
2023-05-24arm64: dts: qcom: ipq6018: add unit address to soc nodeKrzysztof Kozlowski1-1/+1
"soc" node is supposed to have unit address: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230420063610.11068-1-krzysztof.kozlowski@linaro.org
2023-05-24arm64: dts: qcom: ipq6018: correct qrng unit addressKrzysztof Kozlowski1-1/+1
Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc/qrng@e1000: simple-bus unit address format error, expected "e3000" Fixes: 5bf635621245 ("arm64: dts: ipq6018: Add a few device nodes") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230419211856.79332-1-krzysztof.kozlowski@linaro.org
2023-05-24arm64: dts: qcom: Make -cells decimalAndrew Halaney1-1/+1
The property logically makes sense in decimal, and is the standard used elsewhere. Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Andrew Halaney <ahalaney@redhat.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230501212446.2570364-3-ahalaney@redhat.com
2023-05-17arm64: dts: qcom: add missing cache propertiesKrzysztof Kozlowski1-0/+1
Add required cache-level and cache-unified properties to fix warnings like: qdu1000-idp.dtb: l3-cache: 'cache-unified' is a required property qdu1000-idp.dtb: l2-cache: 'cache-level' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230416101134.95686-3-krzysztof.kozlowski@linaro.org
2023-05-17arm64: dts: qcom: use decimal for cache levelKrzysztof Kozlowski1-1/+1
Cache level is by convention a decimal number, not hex. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230416101134.95686-2-krzysztof.kozlowski@linaro.org
2023-03-15arm64: dts: qcom: ipq6018: Fix the PCI I/O port rangeManivannan Sadhasivam1-2/+2
For 64KiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x10000. Hence, fix the bogus PCI address (0x20200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: 095bbdd9a5c3 ("arm64: dts: qcom: ipq6018: Add pcie support") Reported-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230228164752.55682-7-manivannan.sadhasivam@linaro.org
2023-02-13arm64: dts: qcom: ipq6018: align RPM G-Link node with bindingsKrzysztof Kozlowski1-1/+1
Bindings expect (and most of DTS use) the RPM G-Link node name to be "rpm-requests". Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230208101545.45711-1-krzysztof.kozlowski@linaro.org
2023-01-18arm64: dts: qcom: ipq6018: Use lowercase hexKonrad Dybcio1-1/+1
One value escaped my previous lowercase hexification. Take care of it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-6-konrad.dybcio@linaro.org
2023-01-18arm64: dts: qcom: ipq6018: Add/remove some newlinesKonrad Dybcio1-14/+12
Some lines were broken very aggresively, presumably to fit under 80 chars and some places could have used a newline, particularly between subsequent nodes. Address all that and remove redundant comments near PCIe ranges while at it so as not to exceed 100 chars needlessly. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-5-konrad.dybcio@linaro.org
2023-01-18arm64: dts: qcom: ipq6018: Sort nodes properlyKonrad Dybcio1-260/+260
Order nodes by unit address if one exists and alphabetically otherwise. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-4-konrad.dybcio@linaro.org
2023-01-18arm64: dts: qcom: ipq6018: Fix up indentationKonrad Dybcio1-22/+22
The dwc3 subnode was indented using spaces for some reason and other properties were not exactly properly indented. Fix it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-3-konrad.dybcio@linaro.org
2023-01-18arm64: dts: qcom: ipq6018: Pad addresses to 8 hex digitsKonrad Dybcio1-12/+12
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-2-konrad.dybcio@linaro.org
2022-12-27arm64: dts: qcom: ipq6018: Use lowercase hexKonrad Dybcio1-4/+4
Use lowercase hex, as that's the preferred and overwhermingly present style. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221212111037.98160-2-konrad.dybcio@linaro.org
2022-12-06arm64: dts: qcom: ipq6018: improve pcie phy pcs reg tableChristian Marangi1-1/+2
This is not a fix on its own but more a cleanup. Phy qmp pcie driver currently have a workaround to handle pcs_misc not declared and add 0x400 offset to the pcs reg if pcs_misc is not declared. Correctly declare pcs_misc reg and reduce PCS size to the common value of 0x1f0 as done for every other qmp based pcie phy device. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221103212125.17156-2-ansuelsmth@gmail.com
2022-10-17arm64: dts: qcom: ipq6018: move ARMv8 timer out of SoC nodeRobert Marko1-8/+8
The ARM timer is usually considered not part of SoC node, just like other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning: arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'} From schema: dtschema/schemas/simple-bus.yaml Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220927201218.1264506-2-robimarko@gmail.com
2022-10-17arm64: dts: qcom: ipq6018: fix NAND node nameRobert Marko1-1/+1
Per schema it should be nand-controller@79b0000 instead of nand@79b0000. Fix it to match nand-controller.yaml requirements. Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220927201218.1264506-1-robimarko@gmail.com
2022-10-17arm64: dts: qcom: ipq6018: align TLMM pin configuration with DT schemaKrzysztof Kozlowski1-2/+2
DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221006124659.217540-3-krzysztof.kozlowski@linaro.org
2022-09-13arm64: dts: qcom: ipq6018: switch TCSR mutex to MMIOKrzysztof Kozlowski1-9/+4
The TCSR mutex bindings allow device to be described only with address space (so it uses MMIO, not syscon regmap). This seems reasonable as TCSR mutex is actually a dedicated IO address space and it also fixes DT schema checks: qcom/ipq6018-cp01-c1.dtb: hwlock: 'reg' is a required property qcom/ipq6018-cp01-c1.dtb: hwlock: 'syscon' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220909092035.223915-12-krzysztof.kozlowski@linaro.org
2022-09-13arm64: dts: qcom: ipq6018: add missing TCSR syscon compatibleKrzysztof Kozlowski1-1/+1
TCSR syscon node should come with dedicated compatible. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220909092035.223915-6-krzysztof.kozlowski@linaro.org
2022-07-06arm64: dts: qcom: ipq6018: drop USB PHY clock indexJohan Hovold1-1/+1
The QMP USB PHY provides a single clock so drop the redundant clock index. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-4-johan+linaro@kernel.org
2022-07-06arm64: dts: qcom: extend scm compatible stringsDavid Heidelberg1-1/+1
First device specific compatible, then general one. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220626183247.142776-2-david@ixit.cz
2022-07-02arm64: dts: qcom: ipq6018: correct QUP peripheral labelsRobert Marko1-4/+4
Current QUP peripheral labels like spi_0 and i2c_0 dont really tell what is the exact QUP HW being used as there are actually 6 identical QUP HW blocks for UART, SPI and I2C. For example current i2c_0 label actually points to the QUP2 I2C HW. This style of labeling does not follow what the rest of Qualcomm SoC-s use, for example IPQ8074 which has the identical QUP blocks. It also makes it really hard to add the missing QUP DT nodes as there are multiple missing. So utilize the same style as other Qualcomm SoC-s are using and update the CP01 DTS as its the current sole user of them. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220604153003.55172-1-robimarko@gmail.com
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