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2023-12-21drm/xe/selftests: consider multi-GT for eviction testMatthew Auld1-4/+8
We need to sanitize and reset each GT, since xe_bo_evict_all() will evict everything regardless of GT, which can leave other GTs in a broken state. Signed-off-by: Matthew Auld <[email protected]> Cc: Nirmoy Das <[email protected]> Reviewed-by: Nirmoy Das <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/pm: Use PM functions only if CONFIG_PM_SLEEP is enabledFrancois Dugast1-23/+25
This fixes the build without CONFIG_PM_SLEEP such as for riscv. Signed-off-by: Francois Dugast <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Fix array of bindsMatthew Brost1-206/+212
If multiple bind ops in an array of binds touch the same address range invalid GPUVA operations are generated as each GPUVA operation is generated based on the orignal GPUVA state. To fix this, after each GPUVA operations is generated, commit the GPUVA operation updating the GPUVA state so subsequent bind ops can see a current GPUVA state. Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Matthew Brost <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/gpuva: Add drm_gpuva_for_each_op_reverseMatthew Brost1-0/+10
Add a helper to walk op list in reverse. Xe will make use of this when unwinding GPUVA operations. v2: (Rodrigo) reword commit message Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Matthew Brost <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Fixup unwind on VM ops errorsMatthew Brost2-10/+24
Remap ops have 3 parts: unmap, prev, and next. The commit step can fail on any of these. Add a flag for each to these so the unwind is only done the steps that have been committed. v2: (Rodrigo) Use bit macros Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Matthew Brost <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Convert xe_vma_op_flags to BIT macrosMatthew Brost1-3/+3
Rather than open code the shift for values, use BIT macros. Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Matthew Brost <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: fix has_llc on rklMatthew Auld1-0/+1
Matches i915. Assumption going forward is that non-llc + igpu is only a thing on MTL+ which should have explicit coherency pat_index settings for COH_NONE, 1WAY and 2WAY. Signed-off-by: Matthew Auld <[email protected]> Cc: Pallavi Mishra <[email protected]> Cc: Lucas De Marchi <[email protected]> Cc: Matt Roper <[email protected]> Reviewed-by: Matt Roper <[email protected]> Reviewed-by: Pallavi Mishra <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: nuke GuC on unloadMatthew Auld5-7/+25
On PVC unloading followed by reloading the module often results in a completely dead machine (seems to be plaguing CI). Resetting the GuC like we do at load seems to cure it at least when locally testing this. v2: - Move pc_fini into guc_fini. We want to do the GuC reset just after calling pc_fini, otherwise we encounter communication failures. It also seems like a good idea to do the reset before we start releasing the various other GuC resources. In the case of pc_fini there is an explicit stop, but for other stuff like logs, ads, ctb there is not. References: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/542 References: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/597 Signed-off-by: Matthew Auld <[email protected]> Cc: Matthew Brost <[email protected]> Cc: Rodrigo Vivi <[email protected]> Reviewed-by: Matthew Brost <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Prevent return with locked vmPallavi Mishra1-11/+11
Reorder vm_id check after the one for VISIBLE_VRAM. This should prevent returning with locked vm in error scenario. Signed-off-by: Pallavi Mishra <[email protected]> Cc: Matthew Auld <[email protected]> Reviewed-by: Matthew Brost <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Add patch version on guc firmware initZhanjun Dong2-6/+9
Add patch version info on GuC firmware init. This is required info for GuC log decoder. Signed-off-by: Zhanjun Dong <[email protected]> Reviewed-by: Daniele Ceraolo Spurio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/pvc: Use fast copy engines as migrate engine on PVCNiranjana Vishwanathapura3-5/+34
Some copy hardware engine instances are faster than others on PVC. Use a virtual engine of these plus the reserved instance for the migrate engine on PVC. The idea being if a fast instance is available it will be used and the throughput of kernel copies, clears, and pagefault servicing will be higher. v2: Use OOB WA, use all copy engines if no WA is required Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Matthew Brost <[email protected]> Signed-off-by: Niranjana Vishwanathapura <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/pvc: Force even num engines to use 64BNiranjana Vishwanathapura2-0/+11
Wa_16017236439 requires that we update BCS_SWCTRL (via indirect context batch buffer) to set 64B transfers when running on an even-numbered BCS engine and 256B on an odd-numbered BCS engine. v2: Move WA from engine_was[] to lrc_was[] Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Tejas Upadhyay <[email protected]> Signed-off-by: Niranjana Vishwanathapura <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/pvc: Blacklist BCS_SWCTRL registerNiranjana Vishwanathapura2-0/+8
Wa_16017236439 requires the BCS_SWCTRL to be privileged. v2: Define and use BCS_SWCTRL() Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Niranjana Vishwanathapura <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/ct: fix resv_space printMatthew Auld1-1/+1
Actually print the info.resv_space. Signed-off-by: Matthew Auld <[email protected]> Cc: Rodrigo Vivi <[email protected]> Reviewed-by: Matthew Brost <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: standardize vm-less kernel submissionsDaniele Ceraolo Spurio7-37/+12
The current only submission in the driver that doesn't use a vm is the WA setup. We still pass a vm structure (the migration one), but we don't actually use it at submission time and we instead have an hack to use GGTT for this particular engine. Instead of special-casing the WA engine, we can skip providing a VM and use that as selector for whether to use GGTT or PPGTT. As part of this change, we can drop the special engine flag for the WA engine and switch the WA submission to use the standard job functions instead of dedicated ones. v2: rebased on s/engine/exec_queue Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Cc: Matthew Brost <[email protected]> Reviewed-by: Matthew Brost <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: split kernel vs permanent engine flagsDaniele Ceraolo Spurio4-13/+27
If an engine is only destroyed on driver unload, we can skip its clean-up steps with the GuC because the GuC is going to be tuned off as well, so it doesn't matter if we're in sync with it or not. Currently, we apply this optimization to all engines marked as kernel, but this stops us to supporting kernel engines that don't stick around until unload. To remove this limitation, add a separate flag to indicate if the engine is expected to only be destryed on driver unload and use that to trigger the optimzation. While at it, add a small comment to explain what each engine flag represents. v2: s/XE_BUG_ON/XE_WARN_ON, s/ENGINE/EXEC_QUEUE v3: rebased Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Cc: Matthew Brost <[email protected]> Reviewed-by: Matthew Brost <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: fix submissions without vmDaniele Ceraolo Spurio3-5/+8
Kernel queues can submit privileged batches directly in GGTT, so they don't always need a vm. The submission front-end already supports creating and submitting jobs without a vm, but some parts of the back-end assume the vm is always there. Fix this by handling a lack of vm in the back-end as well. v2: s/XE_BUG_ON/XE_WARN_ON, s/engine/exec_queue Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Cc: Matthew Brost <[email protected]> Reviewed-by: Matthew Brost <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Drop xe_mmio_write64()Matt Roper2-14/+0
The only possible 64-bit register writes in the driver come from the highly questionable MMIO ioctl. That ioctl's register write support only operates for userspace running as root and cannot be used by any real userspace; it exists solely to support the "xe_reg" debug tool in IGT. Since the spec indicates that hardware does not officially support 64-bit register accesses, there's no reason to allow such 64-bit writes, even for debugging. Bspec: 60027 Reviewed-by: Lucas De Marchi <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Avoid 64-bit register readsMatt Roper3-16/+58
Intel hardware officially only supports GTTMMADR register accesses of 32-bits or less (although 64-bit accesses to device memory and PTEs in the GSM are fine). Even though we do usually seem to get back reasonable values when performing readq() operations on registers in BAR0, we shouldn't rely on this violation of the spec working consistently. It's likely that even when we do get proper register values back the hardware is internally satisfying the request via a non-atomic sequence of two 32-bit reads, which can be problematic for timestamps and counters if rollover of the lower bits is not considered. Replace xe_mmio_read64() with xe_mmio_read64_2x32() that implements 64-bit register reads as two 32-bit reads and attempts to ensure that the upper dword has stabilized to avoid problematic rollovers for counter and timestamp registers. v2: - Move function from xe_mmio.h to xe_mmio.c. (Lucas) - Convert comment to kerneldoc and note that it shouldn't be used on registers where reads may trigger side effects. (Lucas) Bspec: 60027 Reviewed-by: Lucas De Marchi <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/lnl: Hook up MOCS tableBalasubramani Vivekanandan1-0/+8
LNL uses the Xe2 MOCS table introduced in an earlier patch. Bspec: 71582 Cc: Matt Roper <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/lnl: Add GuC firmware definitionMatt Roper1-0/+1
Define the GuC firmware to load on the platform. Cc: Balasubramani Vivekanandan <[email protected]> Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Matthew Brost <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/lnl: Add LNL platform definitionMatt Roper3-0/+12
LNL is an integrated GPU based on the Xe2 architecture. Bspec: 70821 Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Balasubramani Vivekanandan <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Program GuC's MOCS on Xe2 and beyondMatt Roper2-2/+2
As with PVC, Xe2 platforms require that the index of an uncached MOCS entry be programmed into the GUC_SHIM_CONTROL register. This will likely be needed on future platforms as well. Xe2 also extends the size of the MOCS index register field from two bits to four bits. Since these extra bits were unused on PVC, it should be safe to just increase the size of the mask. Bspec: 60592 Cc: Haridhar Kalvala <[email protected]> Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Balasubramani Vivekanandan <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Add MOCS tableBalasubramani Vivekanandan1-6/+23
Additional minor change to remove L4_2_RESERVED, which will never be required. v2: Make L3/L4 names consistent for GLOB_MOCS defines (Matt Roper) Bspec: 71582 Cc: Matt Roper <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Track VA bits independently of max page table levelMatt Roper5-3/+11
Starting with Xe2, a 5-level page table is always used, regardless of the actual virtual address range supported by the platform. The two values need to be tracked separately in the device descriptor since Xe2 platforms only have a 48 bit virtual address range. Bspec: 59505, 65637, 70817 Cc: Balasubramani Vivekanandan <[email protected]> Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Balasubramani Vivekanandan <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Define Xe2_LPM IP featuresMatt Roper1-0/+7
Xe2_LPM media is represented by GMD_ID value 20.00. It provides 1 VD + 1 VE + 1 SFC. Bspec: 70821, 70819 Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Balasubramani Vivekanandan <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Define Xe2_LPG IP featuresMatt Roper1-0/+19
Define a common set of Xe2 graphics feature flags and definitions that will be used for all platforms in this family. Several of the feature flags are inherited unchanged from Xe_HP and/or Xe_HPC platforms: - dma_mask_size remains 46 (Bspec 70817) - supports_usm=1 (Bspec 59651) - has_flatccs=1 (Bspec 58797) - has_asid=1 (Bspec 59654, 59265, 60288) - has_range_tlb_invalidate=1 (Bspec 71126) However some of them still need proper implementation in the driver to be used, so they are disabled. Notable Xe2-specific changes: - All Xe2 platforms use a five-level page table, regardless of the virtual address space for the platform. (Bspec 59505) The graphics engine mask represents the Xe2 architecture engines (Bspec 60149), but individual platforms may have a reduced set of usable engines, as reflected by their fusing. Cc: Balasubramani Vivekanandan <[email protected]> Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Balasubramani Vivekanandan <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: AuxCCS is no longer usedMatt Roper1-2/+4
Starting with Xe2, all platforms (including igpu platforms) use FlatCCS compression rather than AuxCCS. Similar to PVC, any future platforms that don't support FlatCCS should not attempt to fall back to AuxCCS programming. Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Balasubramani Vivekanandan <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Handle fused-off CCS enginesMatt Roper2-1/+29
On Xe2 platforms, availability of the CCS engines is reflected in the FUSE4 register. Bspec: 62483 Cc: Balasubramani Vivekanandan <[email protected]> Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Matt Atwood <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Update context image layoutsMatt Roper1-2/+74
Engine register state layout has changed a bit on Xe2. We'll also explicitly define a BCS layout to ensure BLIT_SWCTL and BLIT_CCTL are included. Bspec: 65182, 60184, 55793 Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Matt Atwood <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Add MCR register steering for media GTMatt Roper1-2/+24
Xe2 media has a few types of MCR registers, but all except for "GPMXMT" can safely steer to instance 0,0. GPMXMT follows the same rules that MTL's OADDRM ranges did, so it can re-use the same enum value. Bspec: 71186 Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Matt Atwood <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Add MCR register steering for primary GTMatt Roper3-1/+51
Xe2 uses the same steering control register and steering semaphore register as MTL. As with recent platforms, group/instance 0,0 is sufficient to target a non-terminated instance for most classes of MCR registers; the only types of ranges that need to consider platform fusing to find a non-terminated instance are SLICE/DSS ranges and a new SQIDI_PSMI type of range. Note that the range of valid bits in XE2_NODE_ENABLE_MASK may be reduced for some Xe2 SKUs. However the lowest bits are always valid and only the lowest instance is obtained via __ffs(), so there's no need to complicate the masking with extra platform/subplatform checks. Also note that Wa_14017387313 suggests skipping MCR lock acquisition around GAM and GAMWKR registers to prevent MCR register accesses in an interrupt handler from deadlocking when the steering semaphore is already held outside the interrupt context. At this time Xe never issues MCR accesses from within an interrupt handler so the workaround is not currently needed. v2: - [0x008700-0x0087FF] range to extend up to 0x887F (Matt Attwood) - [0x00EF00-0x00F4FF] -> [0x00F000, 0xFFFF] to follow latest bspec version (Bala) Bspec: 71185 Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Matt Atwood <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Add GT topology readoutMatt Roper3-6/+15
Xe2 platforms have three DSS fuse registers for both geometry and compute. Bspec: 67171, 67537, 67401, 67536 Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Matt Atwood <[email protected]> Reviewed-by: Balasubramani Vivekanandan <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Update render/compute context image sizesMatt Roper1-1/+8
The render and compute context are significantly smaller on Xe2 than on previous platforms. Registers: - Render: 3008 dwords -> 12032 bytes -> round to 3 pages - Compute: 1424 dwords -> 5696 bytes -> round to 2 pages We also allocate one additional page for the HWSP, so the total allocation sizes for render and compute are 4 and 3 pages respectively. Bspec: 65182, 56578, 55793 Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Matt Atwood <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Stop tracking 4-tile supportMatt Roper2-11/+1
The choice of Y-major tiling format (either the legacy "TileY" or the newer "Tile4") is based on graphics IP version (12.50 and beyond have Tile4, earlier platforms have TileY). The tracking in xe was originally added to allow re-using display from i915. However as of i915 commit 4ebf43d0488f ("drm/i915: Eliminate has_4tile feature flag"), the display code determines TileY vs Tile4 itself, so this can be removed from xe. Reviewed-by: Lucas De Marchi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: enable idle msg and set hysteresis for GSCCSDaniele Ceraolo Spurio2-0/+20
On MTL (and only on MTL) the GSCCS defaults with idle messaging disabled. This means that, once awoken, the GSCCS will never signal its idleness to the GT. To allow the GT to enter the proper low-power state, we need therefore to turn idle messaging on. As part of this, we also need to set a proper hysteresis value for the engine. v2: use MEDIA_VERSION() and CLR() for the RTP rule and action, add reg bit define in descending order (Matt) Bspec: 71496 Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Cc: Vinay Belgaumkar <[email protected]> Cc: Matt Roper <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: don't expose the GSCCS to usersDaniele Ceraolo Spurio1-0/+3
The kernel is the only expected user of the GSCCS, so we don't want to expose it to userspace. Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: GSC forcewake supportDaniele Ceraolo Spurio2-0/+9
The ID for the GSC forcewake domain already exists, but we're missing the register definitions and the domain intialization, so add that in. v2: move reg definition to be in address order (Matt) Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: add GSCCS ring opsDaniele Ceraolo Spurio1-5/+21
Like the BCS, the GSCCS doesn't have any special HW that needs handling when emitting commands, so we can re-use the same emit_job code. To make it clear that this is now a shared low-level function, it has been renamed to use the "simple" postfix, instead of "copy", to indicate that it applies to all engines that don't need any additional engine-specific handling. Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: add GSCCS irq supportDaniele Ceraolo Spurio2-7/+20
The GSCCS has its own enable and mask registers. The interrupt identity for the GSCCS shows OTHER_CLASS instance 6. Bspec: 54029, 54030 Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: base definitions for the GSCCSDaniele Ceraolo Spurio8-6/+18
The first step in introducing the GSCCS is to add all the basic defs for it (name, mmio base, class/instance, lrc size etc). Bspec: 60149, 60421, 63752 Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: common function to assign queue nameDaniele Ceraolo Spurio4-38/+26
The queue name assignment is identical in both GuC and execlists backends, so we can move it to a common function. This will make adding a new entry in the next patch slightly cleaner. Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Add CONFIG_DRM_XE_PREEMPT_TIMEOUTNiranjana Vishwanathapura3-1/+17
Allow preemption timeout to be specified as a config option. v2: Change unit to microseconds (Tejas) v3: Remove get_default_preempt_timeout() Reviewed-by: Tejas Upadhyay <[email protected]> Signed-off-by: Niranjana Vishwanathapura <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Simplify engine class sched_props settingNiranjana Vishwanathapura1-14/+12
Shortens the too long code lines. Reviewed-by: Tejas Upadhyay <[email protected]> Signed-off-by: Niranjana Vishwanathapura <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/dg2: Remove Wa_15010599737Shekhar Chauhan2-7/+0
Since this is specific to DirectX, we don't need it on Linux. Signed-off-by: Shekhar Chauhan <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Improve vram info debug printingOak Zeng1-5/+6
Print both device physical address range and CPU io range of vram. Also print vram's actual size, usable size excluding stolen memory, and CPU io accessible size. V1: - Add back small BAR device info (Matt) Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Michael J. Ruhl <[email protected]> Reviewed-by: Matthew Brost <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Make xe_mem_region structOak Zeng4-60/+47
Make a xe_mem_region structure which will be used in the coming patches. The new structure is used in both xe device level (xe->mem.vram) and xe_tile level (tile->vram). Make the definition of xe_mem_region.dpa_base to be the DPA base of this memory region and change codes according to this new definition. v1: - rename xe_mem_region.base to dpa_base per conversation with Mike Ruhl Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Michael J. Ruhl <[email protected]> Reviewed-by: Matthew Brost <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Call __guc_exec_queue_fini_async direct for KERNEL exec_queuesMatthew Brost1-14/+6
Usually we call __guc_exec_queue_fini_async via a worker as the exec_queue fini can be done from within the GPU scheduler which creates a circular dependency without a worker. Kernel exec_queues are fini'd at driver unload (not from within the GPU scheduler) so it is safe to directly call __guc_exec_queue_fini_async. Suggested-by: Oded Gabbay <[email protected]> Signed-off-by: Matthew Brost <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: skip rebind_list if vma destroyedMatthew Auld2-4/+7
If we are closing a vm, mark each vma as XE_VMA_DESTROYED and skip touching the rebind_list if this is seen on the eviction path. That way we can safely drop the vm dma-resv lock on the close path without needing to worry about racing with the eviction path trying to add stuff to the rebind_list which can corrupt our contended list, since the destroy and rebind links are the same list entry underneath. References: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/514 Signed-off-by: Matthew Auld <[email protected]> Cc: Matthew Brost <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/guc_submit: fixup deregister in job timeoutMatthew Auld1-4/+6
Rather check if the engine is still registered before proceeding with deregister steps. Also the engine being marked as disabled doesn't mean the engine has been disabled or deregistered from GuC pov, and here we are signalling fences so we need to be sure GuC is not still using this context. v2: - Drop the read_stopped() for this path. Since we are signalling fences on error here, best play it safe and wait for the GT reset to mark the engine as disabled, rather than it just being queued. v3 (Matt Brost): - Keep the read_stopped() on the wait event, since there is no need to wait for an already scheduled GT reset. If it is set we can then just bail without signalling anything. Signed-off-by: Matthew Auld <[email protected]> Cc: Matthew Brost <[email protected]> Reviewed-by: Matthew Brost <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
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