diff options
| author | Niranjana Vishwanathapura <[email protected]> | 2023-08-17 09:20:44 +0000 |
|---|---|---|
| committer | Rodrigo Vivi <[email protected]> | 2023-12-21 11:40:27 -0500 |
| commit | 25063811d9c1f32c3223c27cafc0a95e7a86be26 (patch) | |
| tree | 831c49e9648d4140e01f62af60bd8034fd00ff2a | |
| parent | 429d56a6b12c4a00d22dcc8a1ac0394906c92b67 (diff) | |
drm/xe/pvc: Blacklist BCS_SWCTRL register
Wa_16017236439 requires the BCS_SWCTRL to be privileged.
v2: Define and use BCS_SWCTRL()
Reviewed-by: Matt Roper <[email protected]>
Signed-off-by: Niranjana Vishwanathapura <[email protected]>
Signed-off-by: Rodrigo Vivi <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_engine_regs.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_reg_whitelist.c | 6 |
2 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h index d57fd855086a..1a366d8070f3 100644 --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h @@ -63,6 +63,8 @@ #define RING_BBADDR(base) XE_REG((base) + 0x140) #define RING_BBADDR_UDW(base) XE_REG((base) + 0x168) +#define BCS_SWCTRL(base) XE_REG((base) + 0x200, XE_REG_OPTION_MASKED) + /* Handling MOCS value in BLIT_CCTL like it was done CMD_CCTL */ #define BLIT_CCTL(base) XE_REG((base) + 0x204) #define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 9) diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c index e83781f9a516..e66ae1bdaf9c 100644 --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c @@ -50,6 +50,12 @@ static const struct xe_rtp_entry_sr register_whitelist[] = { RING_FORCE_TO_NONPRIV_DENY | RING_FORCE_TO_NONPRIV_RANGE_64)) }, + { XE_RTP_NAME("16017236439"), + XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY)), + XE_RTP_ACTIONS(WHITELIST(BCS_SWCTRL(0), + RING_FORCE_TO_NONPRIV_DENY, + XE_RTP_ACTION_FLAG(ENGINE_BASE))) + }, {} }; |