diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2023-08-11 09:06:09 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 11:40:25 -0500 |
| commit | 53497182ddf7a98fc33049d51ac3692c2f8097da (patch) | |
| tree | fe6f420f2188161536d6f7c1df8e68be748da62f | |
| parent | c5fa58146ee0e55ef3e8b28c1aed705c97968336 (diff) | |
drm/xe/xe2: Handle fused-off CCS engines
On Xe2 platforms, availability of the CCS engines is reflected in the
FUSE4 register.
Bspec: 62483
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_gt_regs.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_hw_engine.c | 29 |
2 files changed, 29 insertions, 1 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index 33830cd0df66..271ed0cdbe21 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -152,6 +152,7 @@ /* Fuse readout registers for GT */ #define XEHP_FUSE4 XE_REG(0x9114) +#define CCS_EN_MASK REG_GENMASK(19, 16) #define GT_L3_EXC_MASK REG_GENMASK(6, 4) #define GT_VEBOX_VDBOX_DISABLE XE_REG(0x9140) diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c index 24b5226f1433..dd673a684b70 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine.c +++ b/drivers/gpu/drm/xe/xe_hw_engine.c @@ -550,7 +550,7 @@ static void read_copy_fuses(struct xe_gt *gt) } } -static void read_compute_fuses(struct xe_gt *gt) +static void read_compute_fuses_from_dss(struct xe_gt *gt) { struct xe_device *xe = gt_to_xe(gt); @@ -577,6 +577,33 @@ static void read_compute_fuses(struct xe_gt *gt) } } +static void read_compute_fuses_from_reg(struct xe_gt *gt) +{ + struct xe_device *xe = gt_to_xe(gt); + u32 ccs_mask; + + ccs_mask = xe_mmio_read32(gt, XEHP_FUSE4); + ccs_mask = REG_FIELD_GET(CCS_EN_MASK, ccs_mask); + + for (int i = XE_HW_ENGINE_CCS0, j = 0; i <= XE_HW_ENGINE_CCS3; ++i, ++j) { + if (!(gt->info.engine_mask & BIT(i))) + continue; + + if ((ccs_mask & BIT(j)) == 0) { + gt->info.engine_mask &= ~BIT(i); + drm_info(&xe->drm, "ccs%u fused off\n", j); + } + } +} + +static void read_compute_fuses(struct xe_gt *gt) +{ + if (GRAPHICS_VER(gt_to_xe(gt)) >= 20) + read_compute_fuses_from_reg(gt); + else + read_compute_fuses_from_dss(gt); +} + int xe_hw_engines_init_early(struct xe_gt *gt) { int i; |