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2019-06-21drm/amd/powerplay: allow dc request uclk changehersen wu1-1/+2
when dc set mode or color format in frame buffer change, it may request clock changes, like dispclk, dcfclk, uclk. after smu get clock requests, smu will make decision. Signed-off-by: hersen wu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu: initialize THM & CLK IP registers base addressHawking Zhang1-0/+2
was missed before. Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu: fix PA_SC_FIFO_SIZE for Navi10 (v2)Marek Olšák1-10/+11
Proper size is 0. v2: squash in whitespace fixes (Ernst Sjöstrand) Signed-off-by: Marek Olšák <[email protected]> Reviewed-by: Xiaojie Yuan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: remove unsupport function set_thermal_fan_table for navi10Kevin Wang1-13/+0
the PPSMC_MSG_SetFanTemperatureTarget is not support on navi10 Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: enable BACO feature as WARJack Xiao1-0/+1
It would hit SMU fw bug without BACO enablement when audio driver put audio device to D3 state. Before the bug in SMU fw get fixed, enable BACO feature as WAR. Signed-off-by: Jack Xiao <[email protected]> Acked-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: use pp_feature_mask to control uclk(mclk) dpm enabledKevin Wang1-3/+5
the uclk dpm feature is not work well on all navi10 asic, use pp feature mask module parameter to control it. Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu: add new navi10 DIDstiancyin1-0/+2
Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: tiancyin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: add ppt interface version logtiancyin1-2/+4
Include the interface version as well. Signed-off-by: tiancyin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/gfx10: update to latest golden settingAlex Deucher1-1/+1
Fix UTCL1_CGTT_CLK_CTRL Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/powerplay/vega20: use correct table indexAlex Deucher1-5/+5
Use the SMU_* variant so we look up the correct index. Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/VCN: enable indirect DPG SRAM modeLeo Liu1-0/+3
This is default mode for VCN2.x now Signed-off-by: Leo Liu <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/VCN: implement indirect DPG SRAM modeLeo Liu2-19/+53
SRAM will be programmed by PSP Signed-off-by: Leo Liu <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/VCN: add buffer for indirect SRAM usageLeo Liu2-0/+22
This will be used later for indirect SRAM mode Signed-off-by: Leo Liu <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: disable fw dstate when gfxoff is enabledJack Xiao1-1/+4
SMU FW has bug that it would cause hung when both fw dstate and gfxoff are enabled at the same time. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: update smu11_driver_if_navi10.hJack Xiao1-10/+14
update the smu11_driver_if_navi10.h since navi10 smu fw update to 42.23 Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/psp: add new psp interface for vcn updating sramJack Xiao2-0/+16
PSP leverages the existing fw loading function for vcn updating sram. Signed-off-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/psp: convert ucode id to psp ucode idJack Xiao1-0/+6
Convert ucode id to the corresponding psp ucode id. Signed-off-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu: add corresponding vcn ram ucode idJack Xiao1-0/+2
Add VCN RAM ucode id in corresponding to psp ucode id. Signed-off-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/psp: add new VCN RAM ucode id to pspJack Xiao1-0/+2
PSP supports to program vcn sram by ucode loading interface. Signed-off-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu: enable VCN2.0 DPG modeLeo Liu1-1/+2
It will be the default for VCN2.x family Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/VCN2.0: add DPG pause modeLeo Liu1-0/+70
Pause the DPG when not doing decode Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/VCN2.0: add DPG mode start and stop (v2)Leo Liu1-3/+296
This is for using SRAM directly v2: rebase (Alex) Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/VCN2.0: add direct SRAM read and writeLeo Liu1-0/+48
This will be the basic and used for DPG mode Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/VCN2.0 remove unused Macro and declarationLeo Liu1-2/+0
Just for cleanup Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: simplified od_settings for each asicKevin Wang4-87/+77
the od_settings is asic related data, so move it to asic file. Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: move od_default_setting callback to asic fileKevin Wang4-50/+43
the set default od_setting is asic related function, so move thic code to vega20_ppt file. Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: move od8_setting helper function to vega20_pptKevin Wang3-39/+29
these callback functions is only used for vega20 asic, to be compatible other asics,need to move this code to vega20_ppt file Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: fix clk type name error OD_SCLK OD_MCLKKevin Wang2-10/+10
use sw-smu clk type name to replace legacy clk type name Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: fix deadlock issue for smu_force_performance_levelKevin Wang2-10/+4
the smu->mutex is internal lock resource in sw-smu, some functions will use it at the same time, so it maybe will cause deadlock issue. this patch fix this issue in smu_force_performance_level function. Signed-off-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd: the data retured from PRT is expected to be 0Jack Xiao2-1/+4
The dummy page for returning from PRT resides inside system memory, need set system flag bit in VM_L2_CNTL. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/gfx10: update gfx golden settingstiancyin1-2/+4
add new registers: mmPA_SC_ENHANCE_1, mmTCP_CNTL, update registers: mmDB_DEBUG4, mmUTCL1_CTRL Reviewed-by: Xiaojie Yuan <[email protected]> Signed-off-by: tiancyin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/powerplay: add license to smu11 headerAlex Deucher1-0/+22
Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: add interface to get uclk dpm tablehersen wu2-0/+33
dc needs get uclk dpm table for bandwidth calculation Signed-off-by: hersen wu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: wake up azalia from d3 by sending smu messagehersen wu4-1/+19
this is hw workaround to wake up azalia from d3. display asic and azalia are two different pci devices. while display asic wake from d3, current hw does not send signal to azalia. workaround: display driver ask smu send message to azalia device to let azalia wake up. Defintion of SMU message, like PPSMC_MSG_BacroAudioD3PME, is per asic. It is shared by different OS. Signed-off-by: hersen wu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: notify smu with active display counthersen wu3-7/+20
when dc update clocks via smu, smu needs to know how many displays active. this interface is for dc notify number of active displays to smu. Signed-off-by: hersen wu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: allow dc request uclk changehersen wu1-1/+7
when dc set mode or color format in frame buffer change, it may request clock changes, like dispclk, dcfclk, uclk. after smu get clock requests, smu will make decision. Signed-off-by: hersen wu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: remove smu callback funciton get_mclk(get_sclk)Kevin Wang4-103/+52
remove smu callback: get_mclk, get_sclk. because the function smu_get_dpm_freq_range has the same function. Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: remove smu mutex lock in smu_hw_initKevin Wang1-4/+0
the smu mutex lock is unnecessary in smu hw init. Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: add thermal ctf support for navi10Kevin Wang4-0/+92
add sw-CTF support for navi10 Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: fix no statements in function returning non-voidHawking Zhang1-0/+2
Add missing return (rebase fix). Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: move get_thermal_temperature_range to ppt funcsHawking Zhang3-81/+70
The thermal policy could be ASIC specific ones and depends on structures in pptable. As a result, get_thermal_temperature_range should be implemented as ppt funcs instead of smu funcs Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: move function thermal_get_temperature to veag20_pptKevin Wang2-7/+48
the fcuntion thermal_get_temperature will be access SmuMetrics_t data, the data structure is asic related, so move vega20_ppt to implement. Signed-off-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: move function get_metrics_table to vega20_pptKevin Wang4-39/+42
the SmuMetrics_t table is asic related data structure. so move vega20_ppt file to implement. Signed-off-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: move power_dpm_force_performance_level to amdgpu_smu fileKevin Wang3-48/+43
because this callback is not asic related function, so move it to top code level to support more asic (eg: navi10) Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: enable uclk dpm default on navi10Kevin Wang1-6/+6
enable uclk (mclk) dpm by default on navi10 Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: enable ac/dc feature on navi10Kenneth Feng1-1/+2
enable ac/dc feature on navi10. currently we don't have the case to verify it. Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: enable gfxclk ds,dcefclk ds and fw dstate on navi10Kenneth Feng1-1/+4
on navi10, by default the below four features are enabled. gfxclk deep sleep: enabled and verified fw dstate: enabled and then soc ulv is verified dcefclk deep sleep: enabled and verified. notice that on different boards, due to the minimum dcefclk deep sleep setting in VBIOS, we may not see dcefclk deep sleep kicking in. Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: add sclk sysfs interface support for navi10Kevin Wang1-0/+1
miss sclk support in force_clk_levels function Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Xiaojie Yuan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu: correct reference clock value on navi10Tao Zhou1-1/+1
remove the divisor 4 Signed-off-by: Tao Zhou <[email protected]> Acked-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay/smu11: disable some pp features on navi10 A0 secure boardTao Zhou1-0/+12
disable DPM UCLK and SOC DS on A0 secure board Signed-off-by: Tao Zhou <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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