diff options
| author | Tao Zhou <[email protected]> | 2019-05-13 16:52:22 +0800 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2019-06-21 18:59:31 -0500 |
| commit | c877dff7d97eb59e5a3b54160a6d66454b4e8778 (patch) | |
| tree | b725b04427d2b090a0cff2c4e46be5a1a9da517d | |
| parent | fc419158104c66e8ce12aa4cccabfdb5aff3fc5c (diff) | |
drm/amd/powerplay/smu11: disable some pp features on navi10 A0 secure board
disable DPM UCLK and SOC DS on A0 secure board
Signed-off-by: Tao Zhou <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Reviewed-by: Kevin Wang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index 48ad0d6ac179..071bfe32035b 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -340,6 +340,18 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN) *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT); + /* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */ + if (is_asic_secure(smu)) { + /* only for navi10 A0 */ + if ((adev->asic_type == CHIP_NAVI10) && + (adev->rev_id == 0)) { + *(uint64_t *)feature_mask &= + ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT); + *(uint64_t *)feature_mask &= + ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT); + } + } + return 0; } |