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J7200 common processor board has an onboard mux for selecting whether
the OSPI signals are externally routed to OSPI flash or Hyperflash. The
mux state signal input is tied to WKUP_GPIO0_6 and is used by bootloader
for enabling the corresponding node accordingly. Add pinmux for the same.
Signed-off-by: Vaishnav Achath <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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J721E SoM has a HyperFlash and HyperRam connected to HyperBus memory
controller, add corresponding node, pinmux and partitions for the same.
HyperBus is muxed with OSPI and only one controller can be active at a
time, therefore keep HyperBus node disabled. Bootloader will detect the
external mux state through a wkup gpio and enable the node as required.
Signed-off-by: Vaishnav Achath <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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J721E has a Flash SubSystem that has one OSPI and one HyperBus with
muxed datapath and another independent OSPI. Add DT nodes for HyperBus
controller and keep it disabled and model the data path selection mux as a
reg-mux.
Signed-off-by: Vaishnav Achath <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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MDIO nodes defined in the top-level J721e SoC dtsi files are incomplete
and will not be functional unless they are extended with a pinmux.
As the attached PHY is only known about at the board integration level,
these nodes should only be enabled when provided with this information.
Disable the MDIO nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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Mailbox nodes defined in the top-level AM64x SoC dtsi files are incomplete
and may not be functional unless they are extended with a chosen interrupt
and connection to a remote processor.
As the remote processors depend on memory nodes which are only known at
the board integration level, these nodes should only be enabled when
provided with the above information.
Disable the Mailbox nodes in the dtsi files and only enable the ones that
are actually used on a given board.
Signed-off-by: Andrew Davis <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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PCIe nodes defined in the top-level J721e SoC dtsi files are incomplete
and will not be functional unless they are extended with a SerDes PHY.
And usually only one of the two modes can be used at a time as they
share a SerDes link.
As the PHY and mode is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the PCIe nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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These nodes are example nodes for the PCIe controller in "endpoint" mode.
By default the controller is in "root complex" mode and there is already a
DT node for the same.
Examples should go in the bindings or other documentation.
Remove this node.
Signed-off-by: Andrew Davis <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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Mailbox nodes are now disabled by default. The BeagleBoard AI64 DT
addition went in at around the same time and must have missed that
change so the mailboxes are not re-enabled. Do that here.
Fixes: fae14a1cb8dd ("arm64: dts: ti: Add k3-j721e-beagleboneai64")
Signed-off-by: Andrew Davis <[email protected]>
Reviewed-by: Nishanth Menon <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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eMMC tuning was incomplete earlier, so support for high speed modes was
kept disabled. Remove no-1-8-v property to enable support for high
speed modes for eMMC in J784S4 SoC.
Signed-off-by: Bhavya Kapoor <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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J784S4 has two instances of 8 channel ADCs in MCU domain. Add pinmux
information for both ADC nodes.
Signed-off-by: Bhavya Kapoor <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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J784S4 has two instances of 8 channel ADCs in MCU domain. Add support
for both ADC nodes.
Signed-off-by: Bhavya Kapoor <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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The OLDI-LCD1EVM add on board has Rocktech RK101II01D-CT panel[1] with
integrated touch screen. The integrated touch screen is Goodix GT928.
This panel connects with AM65 GP-EVM[2].
Add DT nodes for these and connect the endpoint nodes with DSS.
[1]: Panel link
https://www.digimax.it/en/tft-lcd/20881-RK101II01D-CT
[2]: AM654 LCD EVM:
https://www.ti.com/tool/TMDSLCD1EVM
Signed-off-by: Jyri Sarha <[email protected]>
Signed-off-by: Nikhil Devshatwar <[email protected]>
[[email protected]: Make cosmetic and 6.4 kernel DTSO syntax changes]
Signed-off-by: Aradhya Bhatia <[email protected]>
Reviewed-by: Tomi Valkeinen <[email protected]>
Reviewed-by: Andrew Davis <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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Update the delay values for various speed modes supported, based on
the revised august 2021 J721E Datasheet.
[1] - Table 7-77. MMC0 DLL Delay Mapping for All Timing Modes and
Table 7-86. MMC1/2 DLL Delay Mapping for All Timing Modes, in
https://www.ti.com/lit/ds/symlink/tda4vm.pdf,
(SPRSP36J – FEBRUARY 2019 – REVISED AUGUST 2021)
Signed-off-by: Bhavya Kapoor <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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Include documentation of the AMC package pin name as well to keep it
consistent with the rest of the pinctrl documentation.
Signed-off-by: Nishanth Menon <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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Add board EEPROM support to device tree
Signed-off-by: Nishanth Menon <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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wkup_uart and main_uart1 on this platform is used by tifs and DM
firmwares. Describe them for completeness including the pinmux.
Signed-off-by: Nishanth Menon <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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Drop an extra EoL
Signed-off-by: Nishanth Menon <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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Looks like a couple of http:// links crept in. Use https instead.
While at it, drop unicode encoded character.
Signed-off-by: Nishanth Menon <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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VTM stands for Voltage Thermal Management. Add the thermal zones.
Six sensors mapping to six thermal zones. Main0, Main1, Main2, Main3,
WKUP1 & WKUP2 domains respectively.
Signed-off-by: Keerthy <[email protected]>
[[email protected]: rebased on v6.3-rc1]
Signed-off-by: Bryan Brattlof <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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VTM stands for Voltage Thermal Management. Add the thermal zones.
Three sensors mapping to 3 thermal zones. MCU, MPU & Main domains
respectively.
Signed-off-by: Keerthy <[email protected]>
[[email protected]: rebased on v6.3-rc1]
Signed-off-by: Bryan Brattlof <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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VTM stands for Voltage Thermal Management. Add the thermal zones.
Five sensors mapping ton 5 thermal zones. WKUP, MPU, C7x, GPU & R5F
respectively.
Signed-off-by: Keerthy <[email protected]>
[[email protected]: rebased on v6.3-rc1]
Signed-off-by: Bryan Brattlof <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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VTM stands for Voltage Thermal Management. Add the thermal zones.
Seven sensors mapping to seven thermal zones. Main0, Main1, Main2, Main3,
Main4, WKUP1 & WKUP2 domains respectively.
Signed-off-by: Keerthy <[email protected]>
[[email protected]: rebased on v6.3-rc1]
Signed-off-by: Bryan Brattlof <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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The am62ax supports a single Voltage and Thermal Management (VTM) device
located in the wakeup domain with three associated temperature monitors
located in various hot spots of the die.
Signed-off-by: Bryan Brattlof <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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The am62x supports a single Voltage and Thermal Management (VTM) module
located in the wakeup domain with two associated temperature monitors
located in hot spots of the die.
Signed-off-by: Bryan Brattlof <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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The am64x supports a single VTM module which is located in the main
domain with two associated temperature monitors located at different hot
spots on the die.
Tested-by: Christian Gmeiner <[email protected]>
Signed-off-by: Bryan Brattlof <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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Add memory reservation for the zap-shader and enable the Adreno SMMU,
GPU clock controller, GMU and the GPU nodes for the SC8280XP CRD and the
Lenovo ThinkPad X13s.
Tested-by: Steev Klimaszewski <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Tested-by: Johan Hovold <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
SC8280XP.
Tested-by: Steev Klimaszewski <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Tested-by: Johan Hovold <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Add pcie-mem interconnect path to sdx55 target.
Signed-off-by: Krishna chaitanya chundru <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Some of the regulators must be always-on to ensure correct operation of
the system, e.g. PM8916 L2 for the LPDDR RAM, L5 for most digital I/O
and L7 for the CPU PLL (strictly speaking the CPU PLL might only need
an active-only vote but this is not supported for regulators in
mainline currently).
The RPM firmware seems to enforce that internally, these supplies stay
on even if we vote for them to power off (and there is no other
processor running). This means it's pointless to keep sending
enable/disable requests because they will just be ignored.
Also, drivers are much more likely to get a wrong impression of the
regulator status, because regulator_is_enabled() will return false when
there are no users, even though the regulator is always on.
Describe this properly by marking the regulators as always-on.
The same changes was already made for MSM8916 in commit 8bbd35771f90
("arm64: dts: qcom: msm8916-pm8916: Mark always-on regulators").
Signed-off-by: Stephan Gerhold <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Right now each MSM8939 device has a huge block of regulator constraints
with allowed voltages for each regulator. For lack of better
documentation these voltages are often copied as-is from the vendor
device tree, without much extra thought.
Unfortunately, the voltages in the vendor device trees are often
misleading or even wrong, e.g. because:
- There is a large voltage range allowed and the actual voltage is
only set somewhere hidden in some messy vendor driver. This is often
the case for pm8916_{l14,l15,l16} because they have a broad range of
1.8-3.3V by default.
- The voltage is actually wrong but thanks to the voltage constraints
in the RPM firmware it still ends up applying the correct voltage.
To have proper regulator constraints it is important to review them in
context of the usage. The current setup in the MSM8939 device trees
makes this quite hard because each device duplicates the standard
voltages for components of the SoC and mixes those with minor
device-specific additions and dummy voltages for completely unused
regulators.
The actual usage of the regulators for the SoC components is in
msm8939-pm8916.dtsi, so it can and should also define the related
voltage constraints. These are not board-specific but defined in the
MSM8939/PM8916 specification. There is no documentation available for
MSM8939 but in practice it's almost identical to MSM8916.
Note that this commit does not make any functional change. All used
regulators still have the same regulator constraints as before. Unused
regulators do not have regulator constraints anymore because most of
these were too broad or even entirely wrong. They should be added back
with proper voltage constraints when there is an actual usage.
The same changes were already made for MSM8916 in commit b0a8f16ae4a0
("arm64: dts: qcom: msm8916: Define regulator constraints next to usage").
Signed-off-by: Stephan Gerhold <[email protected]>
Reviewed-by: Bryan O'Donoghue <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Add the same comment to msm8939-pm8916.dtsi that was added for the
MSM8916 variant in commit f193264986b5 ("arm64: dts: qcom:
msm8916-pm8916: Clarify purpose").
Signed-off-by: Stephan Gerhold <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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The regulator constraints for the MSM8939 devices were originally taken
from Qualcomm's msm-3.10 vendor device tree (for lack of better
documentation). Unfortunately it turns out that Qualcomm's voltages are
slightly off as well and do not match the voltage constraints applied
by the RPM firmware.
This means that we sometimes request a specific voltage but the RPM
firmware actually applies a much lower or higher voltage. This is
particularly critical for pm8916_l11 which is used as SD card VMMC
regulator: The SD card can choose a voltage from the current range of
1.8 - 2.95V. If it chooses to run at 1.8V we pretend that this is fine
but the RPM firmware will still silently end up configuring 2.95V.
This can be easily reproduced with a multimeter or by checking the
SPMI hardware registers of the regulator.
Apply the same change as for MSM8916 in commit 355750828c55 ("arm64:
dts: qcom: msm8916: Fix regulator constraints") and make the voltages
match the actual "specified range" in the PM8916 Device Specification
which is enforced by the RPM firmware.
Signed-off-by: Stephan Gerhold <[email protected]>
Reviewed-by: Bryan O'Donoghue <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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The vendor kernel from Sony does not have regulator-always-on for
pm8916_l6, so we should be able to disable it when setting up the
display properly. Since sony-tulip does not have display set up
currently it should be fine to let the regulator disable until then.
Signed-off-by: Stephan Gerhold <[email protected]>
Reviewed-by: Bryan O'Donoghue <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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msm8939-sony-xperia-kanuti-tulip.dts has several regulator voltages
that do not quite seem to match what is used in the vendor kernel.
In particular:
- l10 is fixed at 2.8V [1, 2]
- l11/l12 are 2.95V max [1]
[1]: https://github.com/sonyxperiadev/kernel/blob/aosp/LA.BR.1.3.3_rb2.14/arch/arm/boot/dts/qcom/msm8939-regulator.dtsi
[2]: https://github.com/sonyxperiadev/kernel/blob/aosp/LA.BR.1.3.3_rb2.14/arch/arm/boot/dts/qcom/msm8939-kanuti_tulip.dtsi#L671C1-L673
Fixes: f1134f738fad ("arm64: dts: qcom: Add msm8939 Sony Xperia M4 Aqua")
Signed-off-by: Stephan Gerhold <[email protected]>
Reviewed-by: Bryan O'Donoghue <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Update for recent changes to msm8916.dtsi in commit a5cf21b14666
("arm64: dts: qcom: msm8916: Disable audio codecs by default") and
make lpass_codec disabled by default for devices that are not using
the audio codec functionality inside MSM8939.
Signed-off-by: Stephan Gerhold <[email protected]>
Reviewed-by: Bryan O'Donoghue <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Update for recent changes to pm8916.dtsi in commit 38218822a72f
("arm64: dts: qcom: pm8916: Move default regulator "-supply"s")
and add the now missing pm8916_codec supplies to msm8939-pm8916.dtsi
as well.
Signed-off-by: Stephan Gerhold <[email protected]>
Reviewed-by: Bryan O'Donoghue <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Enable the PMIC GPIO- and RESIN-connected buttons on the board.
Signed-off-by: Konrad Dybcio <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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x1 lane PCIe slot in the common processor board is enabled and connected to
J721S2 SOM. Add PCIe DT node in common processor board to reflect the
same.
Reviewed-by: Siddharth Vadapalli <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
Signed-off-by: Ravi Gunasekaran <[email protected]>
Reviewed-by: Roger Quadros <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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Add PCIe1 RC device tree node for the single PCIe instance present on
the J721S2.
Reviewed-by: Siddharth Vadapalli <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
Signed-off-by: Ravi Gunasekaran <[email protected]>
Reviewed-by: Roger Quadros <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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J721S2 has an OSPI NOR flash on its SOM connected the OSPI0 instance and a
QSPI NOR flash on the common processor board connected to the OSPI1
instance. Add support for the same
Reviewed-by: Vaishnav Achath <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
Signed-off-by: Ravi Gunasekaran <[email protected]>
Reviewed-by: Roger Quadros <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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The board uses lane 1 of SERDES for USB. Set the mux
accordingly.
The USB controller and EVM supports super-speed for USB0
on the Type-C port. However, the SERDES has a limitation
that up to 2 protocols can be used at a time. The SERDES is
wired for PCIe, eDP and USB super-speed. It has been
chosen to use PCIe and eDP as default. So restrict
USB0 to high-speed mode.
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
Signed-off-by: Ravi Gunasekaran <[email protected]>
Reviewed-by: Roger Quadros <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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Configure first lane to PCIe, the second lane to USB and the last two lanes
to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is
connected to PCIe.
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
Signed-off-by: Ravi Gunasekaran <[email protected]>
Reviewed-by: Roger Quadros <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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Add support for two instance of OSPI in J721S2 SoC.
Reviewed-by: Vaishnav Achath <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
Signed-off-by: Ravi Gunasekaran <[email protected]>
Reviewed-by: Roger Quadros <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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Add dt node for the single instance of WIZ (SERDES wrapper) and
SERDES module shared by PCIe, eDP and USB.
Signed-off-by: Matt Ranostay <[email protected]>
Signed-off-by: Ravi Gunasekaran <[email protected]>
Reviewed-by: Roger Quadros <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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Add support for single instance of USB 3.0 controller in J721S2 SoC.
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
Signed-off-by: Ravi Gunasekaran <[email protected]>
Reviewed-by: Roger Quadros <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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USB0 is a Type-C port with dual data role and power sink.
Signed-off-by: Roger Quadros <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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Reserve memory for remote processors. Two memory regions are reserved
for each remote processor. The first 1Mb region is used for virtio
Vring buffers for IPC and the second region is used for holding
resource table, trace buffer and as external memory to the remote
processor. The mailboxes are also assigned for each remote processor.
Signed-off-by: Hari Nagalla <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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The J784S4 SoCs have four TMS320C71x DSP subsystems in the MAIN voltage
domain. The functionality of these DSP subsystems is similar to the C71x
DSP subsystems on earlier k3 device J721S2. Each subsystem has a 48 KB of
L1D configurable SRAM/Cache and 512 KB of L2 SRAM/Cache. This subsystem
has a CMMU but is not currently used. The inter-processor communication
between the main A72 cores and the C71x DSPs is achieved through shared
memory and mailboxes. Add the DT nodes for these DSP processor sub-systems.
Signed-off-by: Hari Nagalla <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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The J784S4 SoCs have 4 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within
the MCU domain, and the remaining three clusters are present in the
MAIN domain (MAIN_R5FSS0, MAIN_R5FSS1 & MAIN_R5FSS2). The functionality
of the R5FSS is same as the R5FSS functionality on earlier K3 platform
device J721S2. Each of the R5FSS can be configured at boot time to be
either run in a LockStep mode or in an Asymmetric Multi Processing (AMP)
fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled
Memory (TCM) internal memories for each core split between two banks -
ATCM and BTCM (further interleaved into two banks). There are some IP
integration differences from standard Arm R5 clusters such as the absence
of an ACP port, presence of an additional TI-specific Region Address
Translater (RAT) module for translating 32-bit CPU addresses into
larger system bus addresses etc.
Add the DT nodes for the R5F cluster/subsystems, the two R5F cores are
each added as child nodes to the corresponding cluster node. The clusters
are configured to run in LockStep mode by default, with the ATCMs enabled
to allow the R5 cores to execute code from DDR with boot-strapping code
from ATCM. The inter-processor communication between the main A72 cores
and these processors is achieved through shared memory and Mailboxes.
The following firmware names are used by default for these cores, and
can be overridden in a board dts file if needed:
MAIN R5FSS0 Core0: j784s4-main-r5f0_0-fw (both in LockStep and Split modes)
MAIN R5FSS0 Core1: j784s4-main-r5f0_1-fw (needed only in Split mode)
MAIN R5FSS1 Core0: j784s4-main-r5f1_0-fw (both in LockStep and Split modes)
MAIN R5FSS1 Core1: j784s4-main-r5f1_1-fw (needed only in Split mode)
MAIN R5FSS2 Core0: j784s4-main-r5f2_0-fw (both in LockStep and Split modes)
MAIN R5FSS2 Core1: j784s4-main-r5f2_1-fw (needed only in Split mode)
MCU R5FSS0 Core0: j784s4-mcu-r5f0_0-fw (needed only in Split mode)
MCU R5FSS0 Core1: j784s4-mcu-r5f0_1-fw (needed only in Split mode)
Signed-off-by: Hari Nagalla <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
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Add thermal zones present on MSM8226 SoC.
Signed-off-by: Matti Lehtimäki <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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