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authorAswath Govindraju <[email protected]>2023-03-31 14:30:24 +0530
committerVignesh Raghavendra <[email protected]>2023-06-14 16:12:19 +0530
commitda61731dc7f5d7a676acd81124229b57e6fbe0ef (patch)
tree03f22fbf16e4e9181b685d9349d8b649b90ed99a
parent80cfbf2f4ac735ab8e72a3c70188c433f06810c1 (diff)
arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0
Configure first lane to PCIe, the second lane to USB and the last two lanes to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is connected to PCIe. Signed-off-by: Aswath Govindraju <[email protected]> Signed-off-by: Matt Ranostay <[email protected]> Signed-off-by: Ravi Gunasekaran <[email protected]> Reviewed-by: Roger Quadros <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vignesh Raghavendra <[email protected]>
-rw-r--r--arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts23
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 1299c715f34c..30a566fef195 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -9,6 +9,9 @@
#include "k3-j721s2-som-p0.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/mux/ti-serdes.h>
/ {
compatible = "ti,j721s2-evm", "ti,j721s2";
@@ -321,6 +324,26 @@
phy-handle = <&phy0>;
};
+&serdes_ln_ctrl {
+ idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>,
+ <J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>;
+};
+
+&serdes_refclk {
+ clock-frequency = <100000000>;
+};
+
+&serdes0 {
+ status = "okay";
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
&mcu_mcan0 {
status = "okay";
pinctrl-names = "default";