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Some comedi drivers allow the `scan_end_arg` value of an asynchronous
command to be a multiple (> 1) of the `chanlist_len` although most
require them to be the same value.
`comedi_bytes_per_scan()` is incorrectly using `chanlist_len` as the
length of the scan. Change it to use `scan_end_arg`.
`comedi_nsamples_left()` is incorrectly using `cur_chan` as the current
sample position in the scan (it is actually the current position in the
channel list). Change it to use the actual sample position in the scan.
(Unfortunately we only have the current scan position in bytes currently,
so convert that to a sample position.)
Signed-off-by: Ian Abbott <[email protected]>
Reviewed-by: H Hartley Sweeten <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Change the MODULE_DESCRIPTION to something more useful than the generic
"Comedi low-level driver".
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Reformat the multi-line comments for follow the CodingStyle.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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For aesthetics, rename this define used for the Analog I/O Readback register.
Define the bits of the register.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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For aesthetics, rename this define used for the Analog Configuration register.
Define the bits of the register.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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For aesthetics, rename this define used for the Counter and Digital I/O
Configuration register. Define the bits of the register.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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For aesthetics, rename this define used for the Interrupt and A/D Clock Control
and Status register. Also, rename the defines for the bits of the register.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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For aesthetics, rename this define used for the A/D Status register. Also,
rename the defines for the bits of the register.
The probe code in dmm32at_reset() checks this register to make sure the
S/D1 and S/D0 bits are set. This check actually verifies that the board is
configured (with jumpers on the board) with all the Analog Input channels
operating in single-ended mode. Add a comment about this.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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For aesthetics, rename this define used for the Miscellaneous Control
register. Also, rename the defines for the bits of the register.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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For aesthetics, rename this define used for the FIFO Status register.
Define the bits of the register.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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For aesthetics, rename this define used for the FIFO Control register.
Also, rename the defines used for the bits of this register.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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This driver currently does not use the FIFO. For completeness, define
the offset to the FIFO Depth register.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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For aesthetics, rename this define used to set the DACH[10] bits in
the DAC MSB register to select the D/A channel.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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For aesthetics, rename this define used for the Status / Auxillary Digital
Inputs register. Document the bits in the register.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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For aesthetics, rename these defines used for the D/A LSB/MSB registers.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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For aesthetics, rename these defines used for the A/D Low/High Channel
registers.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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For aesthetics, rename this define used for the Auxillary Digital Output
register. This register is currently not used in the driver. Document the
bits of the register for completeness.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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For aesthetics, rename these defines used for the A/D LSB/MSB registers.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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For aesthetics, rename this define used for the Start A/D Conversion register.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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The Dimond-MM-32-AT board uses an internal 82C55-type digital I/O circuit to
provide the 24 digital I/O lines. The only quirk is the need to set the page
selection bits in the control register to select page 1 addresses.
Instead of duplicating the 8255 code, provide an (*io) callback and use the
8255 module to support this subdevice.
This also removes the need for the private data in this driver.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Introduce a helper function to set the analog input channel scan and range
control registers. Use the new helper in the analog input (*insn_read) and
(*do_cmd) functions.
The extra sanity checks in the (*do_cmd) are not necessary. The cmd->chanlist
will always be valid and the (*do_cmdtest) validates the channel list in
Step 5.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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The 'data' and 'ai_inuse' members in the private data are not used in the
driver. Remove them.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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This function is not necessary. It simply returns the 'ns' value that was
passed to it.
Remove it as well as the unnecessary Step 4 check of the cmd->convert_arg.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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This driver only supports a single convert_src, TRIG_TIMER. Tidy up
the (*do_cmdtest) validation of the cmd->convert_{src,arg}.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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This driver only supports a single scan_begin_src, TRIG_TIMER. Tidy up
the (*do_cmdtest) validation of the cmd->scan_begin_{src,arg}.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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For aesthetics, add some whitespace to the subdevice initialization.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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For aesthetics, factor the board reset and detection code out of the
(*attach) function.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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For aesthetics, rename this function to dmm32at_ai_insn_read().
Get the 'chan' and 'range' from the chanspec when declaring the local
variables. Remove the unecessary masking of the 'chan'.
Remove some unnecessary comments.
Change the final return to 'insn->n' to clarify the return value.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Introduce a helper function to read the two's complement analog input
sample from the hardware and munge it to the offset binary (unsigned)
format that comedi expects. Use the comedi_offset_munge() helper to
munge the data.
Use the new helper in the analog input (*insn_read) and in the interrupt
handler for the async command.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Remove the private data member 'ai_scans_left' and use the comedi_async
'scans_done' to detect the end-of-acquisition.
This also removes the artifical max limit on the cmd->stop_arg.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Currently the AI (*cancel) changes a private data member to cause the
interrupt handler to cancel the async command after the next interrupt.
Move the code that disables the interrupt and terminates the acquisition
from the interrunt handler into dmm32at_ai_cancel() so that the async
command is terminated instantly.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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The comedi core now counts the number of samples added to the async buffer and
detects the end-of-scan and increments the comedi_async 'scans_done' counter.
Remove the private data member 'stop_counter' and use the 'scans_done' member
to detect the end-of-acquisition.
This fixes a possible interger overflow when calculating the value of the
'stop_counter' and removes the need to accumulate the 'total' number of
samples added to the async buffer in pci9111_handle_fifo_half_full().
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Remove the assumption of the sample size by using the comedi_bytes_to_samples()
helper function to convert the number of bytes to the number of samples.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Absorb this simple helper function into interrupt_pci9118_ai_dma().
Remove the unnecessary local variables 'sampls' and 'm'.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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The comedi core now counts the number of samples added to the async buffer and
detects the end-of-scan and increments the comedi_async 'scans_done' counter.
Remove the private data member 'ai_act_scan' and use the 'scans_done' member
to detect the end-of-acquisition.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Use the generic TCW (timer/counter/watchdog) defines for the 8-bit watchdog.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Remove the error return in the (*auto_attach) and allow the driver to
attach to APC-1564 boards that use the PLD Rev 1.0 I/O mapping.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Use the generic TCW (timer/counter/watchdog) defines for the 32-bit counters.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Use the generic TCW (timer/counter/watchdog) defines for the 12-bit timer.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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The TCW (timer/counter/watchdog) devices in the various ADDI-DATA drivers
use a common register map definition. Provide a common generic define for
these registers so they don't have to be replicated in each driver.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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The timer subdevice is currently broken in this driver.
The Rev 1.0 and 2.x versions of the board both have a 12-bit timer. But only
the Rev 2.x boards have the 3 32-bit counters.
Split the current timer subdevice into two separate subdevices:
1) A single channel 12-bit timer subdevice
2) A three channel 32-bit counter subdevice
This represents the hardware correctly and the counters can be disabled on
the Rev 1.0 boards.
Split up the current (*insn_config), (*insn_write), and (*insn_read) so they
only deal with the hardware associated with the subdevice.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Move the defines for the counter registers from the included source
file to the main driver source file.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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The Rev 1.0 APCI-1564 boards do not have counters.
Fix the code in the main driver source so that the I/O accesses to the
counters do not happen if the devpriv->counters member is not initialized.
This does not fix the code in hwdrv_apci1564.c. That code violates the
comedi API and is currently broken.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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The APCI-1564 has different I/O mapping depending on if the PLD revision
is Rev 1.0 or Rev 2.x.
Add a member, 'timer', to the private data for the base address of the
12-bit timer. Fix the register defines so they will work for all PLD
revisions and initialize the devpriv->timer appropriately.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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The APCI-1564 has different I/O mapping depending on if the PLD revision is
Rev 1.0 or Rev 2.x.
Fix the main register defines so they will work for all PLD revisions and
initialie the dev->iobase appropriately. Move the register defines to the
main driver source file.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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The APCI-1564 has different I/O mapping depending on if the PLD revision is
Rev 1.0 or Rev 2.x. The revision can be determined by reading the EEPROM
register at offset 0x00 of PCI BAR 0 and checking the value of bits 7 to 4.
Add this check to apci1564_auto_attach(). Currently this driver is coded
to work with the Rev 2.x I/O mapping. For now, fail the attach if a Rev 1.0
PLD is detected. Document the I/O mapping for both revisions.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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According to ADDI-DATA, the PLD Revision 2.x versions of the APCI-1564 use
PCI BAR 0 for the main registers of the board.
Remove the 'amcc_iobase' member of the private data and use the dev->iobase
to store the base address of PCI BAR 1.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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According to ADDI-DATA, only the PLD Revision 2.x versions of the APCI-1564
have the 3 counters. The base address for these counters is found in PCI BAR 1.
For aesthetics, save this base address in the private data. The dev->iobase
can then be used for the main registers of the board.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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APCI1564_DI_INT_STATUS_REG
The APCI1564_DI_INT_STATUS_REG is located in the PCI BAR 0 I/O space. That
base address is stored in devpriv->amcc_iobase. Use that to correctly read
the register.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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According to ADDI-DATA, the APCI-1564 board has a FPGA with a PCI core, it
does not use an AMCC PCI controller chip.
Remove the amcc_s5933.h include as well as the read of the AMCC_OP_REG_INTCSR
register. That offset would actually read APCI1564_WDOG_STATUS_REG register
in the FPGA which has nothing to do with the interrupt status.
Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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