diff options
| author | Catalin Marinas <[email protected]> | 2012-03-05 11:49:27 +0000 |
|---|---|---|
| committer | Catalin Marinas <[email protected]> | 2012-09-17 13:41:56 +0100 |
| commit | c1cc1552616d0f354d040823151e61634e7ad01f (patch) | |
| tree | 7c9118864bba9fd78aaec954e2f5269dbbc68240 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | 4f04d8f00545110a0e525ae2fb62ab38cb417236 (diff) | |
arm64: MMU initialisation
This patch contains the initialisation of the memory blocks, MMU
attributes and the memory map. Only five memory types are defined:
Device nGnRnE (equivalent to Strongly Ordered), Device nGnRE (classic
Device memory), Device GRE, Normal Non-cacheable and Normal Cacheable.
Cache policies are supported via the memory attributes register
(MAIR_EL1) and only affect the Normal Cacheable mappings.
This patch also adds the SPARSEMEM_VMEMMAP initialisation.
Signed-off-by: Will Deacon <[email protected]>
Signed-off-by: Catalin Marinas <[email protected]>
Acked-by: Tony Lindgren <[email protected]>
Acked-by: Nicolas Pitre <[email protected]>
Acked-by: Olof Johansson <[email protected]>
Acked-by: Santosh Shilimkar <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions