mmc: sdhci-of-aspeed: Fix clock divider calculation

When calculating the clock divider, start dividing at 2 instead of 1.
The divider is divided by two at the end of the calculation, so starting
at 1 may result in a divider of 0, which shouldn't happen.

Signed-off-by: Eddie James <[email protected]>
Reviewed-by: Andrew Jeffery <[email protected]>
Acked-by: Joel Stanley <[email protected]>
Acked-by: Adrian Hunter <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Cc: [email protected] # v5.4+
Signed-off-by: Ulf Hansson <[email protected]>

0 files changed, 0 insertions, 0 deletions