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authorEddie James <[email protected]>2020-07-09 14:57:06 -0500
committerUlf Hansson <[email protected]>2020-07-13 12:17:34 +0200
commitebd4050c6144b38098d8eed34df461e5e3fa82a9 (patch)
tree18acf4eab9daa29a97dd407fb2d043a93476a485
parent11ba468877bb23f28956a35e896356252d63c983 (diff)
mmc: sdhci-of-aspeed: Fix clock divider calculation
When calculating the clock divider, start dividing at 2 instead of 1. The divider is divided by two at the end of the calculation, so starting at 1 may result in a divider of 0, which shouldn't happen. Signed-off-by: Eddie James <[email protected]> Reviewed-by: Andrew Jeffery <[email protected]> Acked-by: Joel Stanley <[email protected]> Acked-by: Adrian Hunter <[email protected]> Link: https://lore.kernel.org/r/[email protected] Cc: [email protected] # v5.4+ Signed-off-by: Ulf Hansson <[email protected]>
-rw-r--r--drivers/mmc/host/sdhci-of-aspeed.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c
index 56912e30c47e..a1bcc0f4ba9e 100644
--- a/drivers/mmc/host/sdhci-of-aspeed.c
+++ b/drivers/mmc/host/sdhci-of-aspeed.c
@@ -68,7 +68,7 @@ static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
if (WARN_ON(clock > host->max_clk))
clock = host->max_clk;
- for (div = 1; div < 256; div *= 2) {
+ for (div = 2; div < 256; div *= 2) {
if ((parent / div) <= clock)
break;
}