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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2021-09-28 14:01:32 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-10-08 15:08:35 +0200 |
| commit | f294a0ea9d12a658ff326bbe0d64137659bc2fc9 (patch) | |
| tree | 63692058ef702cbd0dd38676dc49a08f85afb9b5 /tools/perf/scripts/python/stackcollapse.py | |
| parent | cc3e8f97bbd370b51b3bb7fec391d65d461d7d02 (diff) | |
clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Controller
Add clock and reset entries for SPI Multi I/O Bus Controller.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210928130132.15022-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions