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authorGeert Uytterhoeven <geert+renesas@glider.be>2021-07-02 11:58:05 +0200
committerGeert Uytterhoeven <geert+renesas@glider.be>2021-09-28 09:28:53 +0200
commitcc3e8f97bbd370b51b3bb7fec391d65d461d7d02 (patch)
treea1e55be2f1bf71565e59ba0d643ca1b5655612ee /tools/perf/scripts/python/stackcollapse.py
parentc11d7f5126b7c5da41f8fb7f69fc86fece65b2b3 (diff)
clk: renesas: r8a779a0: Add Z0 and Z1 clock support
Add support for the Z0 and Z1 (Cortex-A76 Sub-system 0 and 1) clocks, based on the existing support for Z clocks on R-Car Gen3. As the offsets of the CPG_FRQCRB and CPG_FRQCRC registers on R-Car V3U differ from the offsets on other R-Car Gen3 SoCs, we cannot use the existing R-Car Gen3 support as-is. For now, just make a copy, and change the register offsets. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/2112e3bc870580c623bdecfeff8c74739699c610.1625219713.git.geert+renesas@glider.be
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