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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2021-09-22 16:51:45 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-09-24 15:11:05 +0200 |
| commit | c11d7f5126b7c5da41f8fb7f69fc86fece65b2b3 (patch) | |
| tree | d96123d909a0ae76a15cbef9f2c5bdf727b3899f /tools/perf/scripts/python/stackcollapse.py | |
| parent | 32897e6fff196a5de4981030466ae391dfe56c7b (diff) | |
clk: renesas: r9a07g044: Add GbEthernet clock/reset
Add ETH{0,1} clock/reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210922155145.28156-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions