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| author | Stephen Boyd <sboyd@kernel.org> | 2021-10-07 20:41:59 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-10-07 20:41:59 -0700 |
| commit | e974872eb3913902d4a4d1f5724c5060210067e3 (patch) | |
| tree | a1e55be2f1bf71565e59ba0d643ca1b5655612ee /tools/perf/scripts/python/stackcollapse.py | |
| parent | 6880fa6c56601bb8ed59df6c30fd390cc5f6dd8f (diff) | |
| parent | cc3e8f97bbd370b51b3bb7fec391d65d461d7d02 (diff) | |
Merge tag 'renesas-clk-for-v5.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add TPU (PWM), and Z (Cortex-A76) clocks on Renesas R-Car V3U
- Add Ethernet clocks on Renesas RZ/G2L
* tag 'renesas-clk-for-v5.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a779a0: Add Z0 and Z1 clock support
clk: renesas: r9a07g044: Add GbEthernet clock/reset
clk: renesas: rzg2l: Add support to handle coupled clocks
clk: renesas: r9a07g044: Add ethernet clock sources
clk: renesas: rzg2l: Add support to handle MUX clocks
clk: renesas: r8a779a0: Add TPU clock
clk: renesas: rzg2l: Fix clk status function
clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK critical
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions