diff options
| author | Mauro Rossi <[email protected]> | 2020-07-10 20:30:01 +0200 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2020-07-27 16:46:28 -0400 |
| commit | d85a1e536ab8cbc9f96f7a0554703887d603c401 (patch) | |
| tree | fe727b7e151aa693932d2542a36503db0e3b84fd /tools/perf/scripts/python/stackcollapse.py | |
| parent | b91f056fb5e192411635ce9e9e81f9f741ea1f5f (diff) | |
drm/amd/display: dce_opp: add DCE6 specific macros,functions
[Why]
DCE6 has no FMT_TRUNCATE_MODE bit in FMT_BIT_DEPTH_CONTROL register
DCE6 has no FMT_CLAMP_COMPONENT_{R,G,B} registers
DCE6 has no FMT_SUBSAMPLING_{MODE,ORDER} bits in FMT_CONTROL register
[How]
Add DCE6 specific macros definitions for OPP registers and masks
DCE6 OPP macros will avoid buiding errors when using DCE6 headers
Add dce60_set_truncation() w/o FMT_TRUNCATE_MODE bit programming
Add dce60_opp_set_clamping() w/o Format Clamp Component programming
Add dce60_opp_program_fmt() w/o Format Subsampling bits programming
Add dce60_opp_program_bit_depth_reduction() with dce60_set_truncation
Use dce60_opp_program_fmt() in dce60_opp_funcs
Use dce60_opp_program_bit_depth_reduction() in dce60_opp_funcs
Add DCE6 specific dce60_opp_construct
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Mauro Rossi <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions