diff options
| author | Mauro Rossi <[email protected]> | 2020-07-10 20:25:01 +0200 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2020-07-27 16:46:26 -0400 |
| commit | b91f056fb5e192411635ce9e9e81f9f741ea1f5f (patch) | |
| tree | 6b679340bb7dd7d26a5bd87b2f8b55a7b5e249cb /tools/perf/scripts/python/stackcollapse.py | |
| parent | c1a64ebd4d13da1ddc4ec7ddc14a0c86a281a7f8 (diff) | |
drm/amd/display: dce_mem_input: add DCE6 specific macros,functions (v2)
[Why]
DCE6 has DPG_PIPE_ARBITRATION_CONTROL3 register for Line Buffer watermark selection
DCE6 has STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK mask for Stutter watermark selection
DCE6 has NB_PSTATE_CHANGE_WATERMARK_MASK mask for North Bridge watermark selection
DCE6 has no GRPH_MICRO_TILE_MODE mask
DCE6 has no HW_ROTATION register
[How]
Add DCE6 specific macros definitions for MI registers and masks
Add DCE6 specific registers to dce_mem_input_registers struct
Add DCE6 specific masks to dce_mem_input_masks struct
DCE6 MI macros/structs changes will avoid buiding errors when using DCE6 headers
Add dce60_program_urgency_watermark() function
Add dce60_program_nbp_watermark() function
Add dce60_program_stutter_watermark() function
Add dce60_mi_program_display_marks() function w/ new DCE6 watermark programming
Add DCE6 specific tiling programming and modify DCE8 case
Add dce60_program_size() fuction w/o Rotation processing
Add dce60_mi_program_surface_config() fuction
Use dce60_mi_program_display_marks() in dce60_mi_funcs
Use dce60_mi_program_surface_config() in dce60_mi_funcs
Add DCE6 specific dce60_mem_input_construct
v2: remove unused variable (Alex)
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Mauro Rossi <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions