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| author | Stephen Boyd <sboyd@kernel.org> | 2021-10-15 14:57:57 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-10-15 14:57:57 -0700 |
| commit | bada0389c2d8c544c4410140bce45aa01aaa59ad (patch) | |
| tree | 0caf91c073ccd8c26c4b1ffce206a66aa36652e1 /tools/perf/scripts/python/stackcollapse.py | |
| parent | e974872eb3913902d4a4d1f5724c5060210067e3 (diff) | |
| parent | 2bd9feed23166f5ab67dec2ca02bd3f74c77b0ba (diff) | |
Merge tag 'renesas-clk-for-v5.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add SPI Multi I/O Bus and SDHI clocks and resets on RZ/G2L
- Add SPI Multi I/O Bus (RPC) clocks on R-Car V3U
- Add MediaLB clocks on R-Car H3, M3-W/W+, and M3-N
* tag 'renesas-clk-for-v5.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a779[56]x: Add MLP clocks
clk: renesas: r9a07g044: Add SDHI clock and reset entries
clk: renesas: rzg2l: Add SDHI clk mux support
clk: renesas: r8a779a0: Add RPC support
clk: renesas: cpg-lib: Move RPC clock registration to the library
clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Controller
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions