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| author | Lad Prabhakar <[email protected]> | 2024-07-30 13:24:36 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2024-08-23 15:43:27 +0200 |
| commit | 833948fb2b63155847ab691a54800f801555429b (patch) | |
| tree | 4785577800e4f0a731695c696f9b504176bdb3aa /tools/perf/scripts/python/stackcollapse.py | |
| parent | 45afa9eacb59b258d2e53c7f63430ea1e8344803 (diff) | |
arm64: dts: renesas: r9a07g044: Correct GICD and GICR sizes
The RZ/G2L(C) SoC is equipped with the GIC-600. The GICD is 64KiB +
64KiB for the MBI alias (in total 128KiB), and the GICR is 128KiB per
CPU.
Fixes: 68a45525297b2 ("arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's")
Signed-off-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions