clk: qoriq: Separate root input clock for core PLLs on ls1012a

ls1012a has separate input root clocks for core PLLs versus the
platform PLL, with the latter described as sysclk in the hw docs.
If a second input clock, named "coreclk", is present, this clock will be
used for the core PLLs.

Signed-off-by: Scott Wood <[email protected]>
Signed-off-by: Tang Yuantian <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

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