diff options
| author | Scott Wood <[email protected]> | 2017-03-20 10:37:22 +0800 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2017-06-01 01:24:10 -0700 |
| commit | 3d362b1fab97dffaf3f6ef55a03c7dcccfa97fd3 (patch) | |
| tree | 1bb319f5bc907e75bf8b4d179ce1b30053b09a58 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 8e56133e5c7b7a7a97f6a92d92f664d5ecd30745 (diff) | |
dt-bindings: qoriq-clock: Add coreclk
ls1012a has separate input root clocks for core PLLs versus the platform
PLL, with the latter described as sysclk in the hw docs.
Update the qoriq-clock binding to allow a second input clock, named
"coreclk". If present, this clock will be used for the core PLLs.
Signed-off-by: Scott Wood <[email protected]>
Signed-off-by: Tang Yuantian <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions