diff options
| author | Biju Das <biju.das.jz@bp.renesas.com> | 2021-10-07 12:14:34 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-10-08 15:10:36 +0200 |
| commit | 373bd6f487562e8727bc842e9983b093d57968cc (patch) | |
| tree | ee3fae4574573a3b47c47aafd688ea8230c5d709 /tools/perf/scripts/python/stackcollapse.py | |
| parent | eaff33646f4cb6a541d01013b0a222f03f6dfac3 (diff) | |
clk: renesas: r9a07g044: Add SDHI clock and reset entries
Add SDHI{0,1} mux, clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211007111434.8665-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions