diff options
| author | Biju Das <biju.das.jz@bp.renesas.com> | 2021-10-07 12:14:33 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-10-08 15:10:36 +0200 |
| commit | eaff33646f4cb6a541d01013b0a222f03f6dfac3 (patch) | |
| tree | 4c13096757ea1502d332605e9e8e809c1e392190 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 27c9d7635d23416f5e791508882f34157dde23f5 (diff) | |
clk: renesas: rzg2l: Add SDHI clk mux support
Add SDHI clk mux support to select SDHI clock from different clock
sources.
As per HW manual, direct clock switching from 533MHz to 400MHz and
vice versa is not recommended. So added support for handling this
in mux.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211007111434.8665-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions