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author | Li Ming <ming4.li@intel.com> | 2024-08-30 06:13:07 +0000 |
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committer | Dave Jiang <dave.jiang@intel.com> | 2024-09-03 15:29:33 -0700 |
commit | c8706cc15a5814becacff778017bbcc5c031490a (patch) | |
tree | acfb1ef80d9db147f8f45b3f170b6a821ad5afd8 /tools/perf/scripts/python/mem-phys-addr.py | |
parent | 577a67662ff529f617981fe9692ff277b5756402 (diff) |
cxl/pci: cxl_dport_map_rch_aer() cleanup
cxl_dport_map_ras() is used to map CXL RAS capability, the RCH AER
capability should not be mapped in the function but should mapped in
cxl_dport_init_ras_reporting(). Moving cxl_dport_map_ras() out of
cxl_dport_map_ras() and into cxl_dport_init_ras_reporting().
In cxl_dport_init_ras_reporting(), the AER capability position in RCRB
will be located but the position is only used in
cxl_dport_map_rch_aer(), getting the position in cxl_dport_map_rch_aer()
rather than cxl_dport_init_ras_reporting() is more reasonable and makes
the code clearer.
Besides, some local variables in cxl_dport_map_rch_aer() are
unnecessary, remove them to make the function more concise.
Signed-off-by: Li Ming <ming4.li@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://patch.msgid.link/20240830061308.2327065-2-ming4.li@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions