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author | Li Ming <ming4.li@intel.com> | 2024-08-30 06:13:06 +0000 |
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committer | Dave Jiang <dave.jiang@intel.com> | 2024-09-03 15:29:33 -0700 |
commit | 577a67662ff529f617981fe9692ff277b5756402 (patch) | |
tree | 2a5cc91adbd3db325112246053a52050c6901a5f /tools/perf/scripts/python/mem-phys-addr.py | |
parent | 91c0e9d6a205ab0e318dc0dc6e72cbbdb21f8094 (diff) |
cxl/pci: Rename cxl_setup_parent_dport() and cxl_dport_map_regs()
The name of cxl_setup_parent_dport() function is not clear, the function
is used to initialize AER and RAS capabilities on a dport, therefore,
rename the function to cxl_dport_init_ras_reporting(), it is easier for
user to understand what the function does. Besides, adjust the order of
the function parameters, the subject of cxl_dport_init_ras_reporting()
is a cxl dport, so a struct cxl_dport as the first parameter of the
function should be better.
cxl_dport_map_regs() is used to map CXL RAS capability on a cxl dport,
using cxl_dport_map_ras() as the function name.
Signed-off-by: Li Ming <ming4.li@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://patch.msgid.link/20240830061308.2327065-1-ming4.li@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions