diff options
| author | Ikjoon Jang <ikjn@chromium.org> | 2024-02-23 17:11:21 +0800 |
|---|---|---|
| committer | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2024-04-03 10:03:38 +0200 |
| commit | 1781f2c461804c0123f59afc7350e520a88edffb (patch) | |
| tree | aa344e3df8d93edbf00fac5560a5e12e9c272b34 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 4cece764965020c22cff7665b18a012006359095 (diff) | |
arm64: dts: mediatek: mt8183: Add power-domains properity to mfgcfg
mfgcfg clock is under MFG_ASYNC power domain.
Fixes: e526c9bc11f8 ("arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile")
Fixes: 37fb78b9aeb7 ("arm64: dts: mediatek: Add mt8183 power domains controller")
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Ikjoon Jang <ikjn@chromium.org>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20240223091122.2430037-1-wenst@chromium.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions