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| author | Kan Liang <kan.liang@linux.intel.com> | 2020-10-19 08:35:26 -0700 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2020-10-29 11:00:40 +0100 |
| commit | cbea56395cba13173fffb9251cb23f146b51c792 (patch) | |
| tree | 8e63128a15d4f330e5fe96b25735687637d5210b /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | b14d0db5b8c86507c9810c1c8162c7d4a3c656bd (diff) | |
perf/x86/cstate: Add Rocket Lake CPU support
From the perspective of Intel cstate residency counters, Rocket Lake is
the same as Ice Lake and Tiger Lake. Share the code with them. Update
the comments for Rocket Lake.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20201019153528.13850-2-kan.liang@linux.intel.com
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions