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| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2024-07-11 15:34:03 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-07-30 10:44:14 +0200 |
| commit | 6f5c16b74b8d2eacc98f4e0d1611a129aa6506bd (patch) | |
| tree | 80a38ba308ef74aa12b55f102f7c9609a885813b /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | 10dfa837da4f5319ef6871c7cc7357da190c482f (diff) | |
clk: renesas: r9a08g045: Add DMA clocks and resets
Add the missing DMA clock and resets.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240711123405.2966302-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions