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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2024-07-09 14:51:42 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-07-30 10:28:39 +0200 |
| commit | 10dfa837da4f5319ef6871c7cc7357da190c482f (patch) | |
| tree | 059c23f5f74e72a6566f7ba6058e017aede7fe69 /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | 23319333146fb856f6e767f419830f6d7114eefc (diff) | |
clk: renesas: r9a07g043: Add LCDC clock and reset entries
Add LCDC clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240709135152.185042-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions