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| author | Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> | 2024-07-04 15:17:20 +0900 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-07-30 10:28:39 +0200 |
| commit | 23319333146fb856f6e767f419830f6d7114eefc (patch) | |
| tree | bbd01d8df57b259e9cf658b3ec5d6edb9f4fcfdd /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | 8400291e289ee6b2bf9779ff1c83a291501f017b (diff) | |
clk: renesas: r8a779h0: Add PCIe clock
Add the PCIe module clock, which is used by the PCIe module on the
Renesas R-Car V4M (R8A779H0) SoC.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240704061720.1444755-1-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions