diff options
author | Yoshihiro Shimoda <[email protected]> | 2024-07-04 15:17:20 +0900 |
---|---|---|
committer | Geert Uytterhoeven <[email protected]> | 2024-07-30 10:28:39 +0200 |
commit | 23319333146fb856f6e767f419830f6d7114eefc (patch) | |
tree | bbd01d8df57b259e9cf658b3ec5d6edb9f4fcfdd | |
parent | 8400291e289ee6b2bf9779ff1c83a291501f017b (diff) |
clk: renesas: r8a779h0: Add PCIe clock
Add the PCIe module clock, which is used by the PCIe module on the
Renesas R-Car V4M (R8A779H0) SoC.
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
-rw-r--r-- | drivers/clk/renesas/r8a779h0-cpg-mssr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index 16a2e26abcc7..bfb55c15b39e 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -195,6 +195,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = { DEF_MOD("msi3", 621, R8A779H0_CLK_MSO), DEF_MOD("msi4", 622, R8A779H0_CLK_MSO), DEF_MOD("msi5", 623, R8A779H0_CLK_MSO), + DEF_MOD("pcie0", 624, R8A779H0_CLK_S0D2_HSC), DEF_MOD("rpc-if", 629, R8A779H0_CLK_RPCD2), DEF_MOD("scif0", 702, R8A779H0_CLK_SASYNCPERD4), DEF_MOD("scif1", 703, R8A779H0_CLK_SASYNCPERD4), |