diff options
| author | Varshini Rajendran <varshini.rajendran@microchip.com> | 2024-07-29 12:38:03 +0530 |
|---|---|---|
| committer | Claudiu Beznea <claudiu.beznea@tuxon.dev> | 2024-08-07 19:16:47 +0300 |
| commit | 3dc73106ffc47640e692b9b32ebfd59d776c07fd (patch) | |
| tree | 5041c91ce2445d578e40c23340331332694d13ca /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | 5bf194adedb921f87fb7c9c59c590b802458bccc (diff) | |
dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DT
Allow PLLADIV2 and LVDSPLL to be referenced as a PMC_TYPE_CORE
clock from phandle in DT for sam9x7 SoC family.
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Link: https://lore.kernel.org/r/20240729070803.1990916-1-varshini.rajendran@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions