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| author | Varshini Rajendran <[email protected]> | 2024-07-29 12:38:03 +0530 |
|---|---|---|
| committer | Claudiu Beznea <[email protected]> | 2024-08-07 19:16:47 +0300 |
| commit | 3dc73106ffc47640e692b9b32ebfd59d776c07fd (patch) | |
| tree | 5041c91ce2445d578e40c23340331332694d13ca /tools/perf/scripts/python | |
| parent | 5bf194adedb921f87fb7c9c59c590b802458bccc (diff) | |
dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DT
Allow PLLADIV2 and LVDSPLL to be referenced as a PMC_TYPE_CORE
clock from phandle in DT for sam9x7 SoC family.
Signed-off-by: Varshini Rajendran <[email protected]>
Acked-by: Rob Herring <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Claudiu Beznea <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions