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| author | Lucas Stach <l.stach@pengutronix.de> | 2024-05-03 17:33:29 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2024-05-04 12:38:13 +0200 |
| commit | f513991b69885025995dcb4ca75d2ee7261e1273 (patch) | |
| tree | e4422b8d1f9fc8354c561bb94274b10a18ed8138 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 947b8f2a8b5155f6e9560af07ed65b3cc9aecd75 (diff) | |
clk: rockchip: rk3568: Add PLL rate for 724 MHz
This rate allows to provide a low-jitter 72,4 MHz pixelclock
for a custom eDP panel from the VPLL.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Link: https://lore.kernel.org/r/20240503153329.3906030-1-l.stach@pengutronix.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions