diff options
| author | Lucas Stach <[email protected]> | 2024-05-03 17:33:29 +0200 |
|---|---|---|
| committer | Heiko Stuebner <[email protected]> | 2024-05-04 12:38:13 +0200 |
| commit | f513991b69885025995dcb4ca75d2ee7261e1273 (patch) | |
| tree | e4422b8d1f9fc8354c561bb94274b10a18ed8138 | |
| parent | 947b8f2a8b5155f6e9560af07ed65b3cc9aecd75 (diff) | |
clk: rockchip: rk3568: Add PLL rate for 724 MHz
This rate allows to provide a low-jitter 72,4 MHz pixelclock
for a custom eDP panel from the VPLL.
Signed-off-by: Lucas Stach <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3568.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 2d44bcaef046..53d10b1c627b 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -64,6 +64,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0), + RK3036_PLL_RATE(724000000, 3, 181, 2, 1, 1, 0), RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0), RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0), RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0), |