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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2022-10-28 17:59:18 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-11-10 16:36:33 +0100 |
| commit | b3e77da00f1b7b670983c69d0295f4ce132bf87c (patch) | |
| tree | 4fa9ce9ce0b3e877e85a77bb888f30dc535717ba /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | b9a0be2054964026aa58966ce9724b672f210835 (diff) | |
riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
Single).
RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
Below are the RZ/Five SoC specific blocks added in the initial DTSI which
can be used to boot via initramfs on RZ/Five SMARC EVK:
- AX45MP CPU
- PLIC
[0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20221028165921.94487-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions