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author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2022-10-25 23:06:29 +0100 |
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committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-10-28 14:23:00 +0200 |
commit | b9a0be2054964026aa58966ce9724b672f210835 (patch) | |
tree | 7fb4452881d85f6e2a62139d1b140feb3a37bf77 /tools/perf/scripts/python/export-to-sqlite.py | |
parent | 49669da644cf000eb79dbede55bd04acf3f2f0a0 (diff) |
arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts
Move RZ/G2UL SoC specific parts to r9a07g043u.dtsi so that
r9a07g043.dtsi can be shared with RZ/Five (RISC-V SoC).
Below are the changes due to which SoC specific parts are moved to
r9a07g043u.dtsi:
- RZ/G2UL has Cortex-A55 (ARM64) whereas RZ/Five has AX45MP (RISC-V),
- RZ/G2UL has GICv3 as interrupt controller whereas RZ/Five has PLIC,
- RZ/G2UL has interrupts for SYSC block whereas interrupts are missing
for SYSC block on RZ/Five,
- RZ/G2UL has armv8-timer whereas RZ/Five has riscv-timer,
- RZ/G2UL has PSCI whereas RZ/Five have OpenSBI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20221025220629.79321-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
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