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| author | Anson Huang <Anson.Huang@nxp.com> | 2018-05-18 09:01:05 +0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-06-01 12:15:21 -0700 |
| commit | 9c7150daffeca95c575be807db8bc8d25d8e5a5f (patch) | |
| tree | 8ee732ee1fc8b441ba6ef3665b840860ddaaa614 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | f93f2ed94a9073b224ca817178562a6281d2eda5 (diff) | |
clk: imx7d: correct enet clock CCGR registers
Correct enet clock gates as below:
CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 and enet2 bus clocks)
CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK
CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK
Just rename unused IMX7D_ENETx_REF_ROOT_CLK for
IMX7D_ENETx_IPG_ROOT_CLK instead of adding new clocks.
Based on Andy Duan's patch from the NXP kernel tree.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions